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authorRich Felker <dalias@libc.org>2016-10-13 15:17:41 -0400
committerRich Felker <dalias@libc.org>2016-10-13 16:20:28 -0400
commit269f737893be34b7bc1fb70eae3309e60d96eac4 (patch)
treee61ac24e5701c7d6a2e8e4f9a1e9496fdcd040b1
parentdf8b4a500473bab0fc26eb1bef7c4cdb60c145ca (diff)
downloadlinux-sh-jcore-4.6.tar.gz
irqchip/jcore: revert to safer fix for percpu irqsjcore-4.6-20161013jcore-4.6
Signed-off-by: Rich Felker <dalias@libc.org>
-rw-r--r--drivers/irqchip/irq-jcore-aic.c29
1 files changed, 19 insertions, 10 deletions
diff --git a/drivers/irqchip/irq-jcore-aic.c b/drivers/irqchip/irq-jcore-aic.c
index 055fb6f1625f..ed4d2339d0eb 100644
--- a/drivers/irqchip/irq-jcore-aic.c
+++ b/drivers/irqchip/irq-jcore-aic.c
@@ -25,21 +25,30 @@
static struct irq_chip jcore_aic;
+/*
+ * The J-Core AIC1 and AIC2 are cpu-local interrupt controllers and do
+ * not distinguish or use distinct irq number ranges for per-cpu event
+ * interrupts (timer, IPI). Since information to determine whether a
+ * particular irq number should be treated as per-cpu is not available
+ * at mapping time, we use a wrapper handler function which chooses
+ * the right handler at runtime based on whether IRQF_PERCPU was used
+ * when requesting the irq.
+ */
+
+static void handle_jcore_irq(struct irq_desc *desc)
+{
+ if (irqd_is_per_cpu(irq_desc_get_irq_data(desc)))
+ handle_percpu_irq(desc);
+ else
+ handle_simple_irq(desc);
+}
+
static int jcore_aic_irqdomain_map(struct irq_domain *d, unsigned int irq,
irq_hw_number_t hwirq)
{
struct irq_chip *aic = d->host_data;
- /*
- * For the J-Core AIC1 and AIC2, all irqs behave as percpu. Some
- * (timer and IPI) can be generated specifically for individual
- * CPUs; the rest are directly connected to a particular CPU. None
- * are dynamically routable. Use handle_percpu_irq for all cases,
- * since it's necessary for the former and safe (and faster) for
- * the latter, and there's no way to distinguish them with the
- * information available at mapping time.
- */
- irq_set_chip_and_handler(irq, aic, handle_percpu_irq);
+ irq_set_chip_and_handler(irq, aic, handle_jcore_irq);
return 0;
}