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authorRich Felker <dalias@libc.org>2016-05-17 23:18:58 +0000
committerRich Felker <dalias@libc.org>2016-06-08 21:54:19 +0000
commit5a0f3177142fbea475b493edc959840979feb84d (patch)
tree7811af28dcc25cc3a16c55e4f79c2b605568fe70
parentb38a325bb18909f3e3f52fa6ef818e8179aededf (diff)
downloadlinux-sh-5a0f3177142fbea475b493edc959840979feb84d.tar.gz
of: add J-Core timer bindings
Signed-off-by: Rich Felker <dalias@libc.org>
-rw-r--r--Documentation/devicetree/bindings/timer/jcore,pit.txt29
1 files changed, 29 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/timer/jcore,pit.txt b/Documentation/devicetree/bindings/timer/jcore,pit.txt
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+J-Core Programmable Interval Timer and Clocksource
+
+Required properties:
+
+- compatible: Must be "jcore,pit".
+
+- reg: Memory region for timer/clocksource registers.
+
+- interrupts: An interrupt to assign for the timer. The actual pit
+ core is integrated with the aic and allows the timer interrupt
+ assignment to be programmed by software, but this property is
+ required in order to reserve an interrupt number that doesn't
+ conflict with other devices.
+
+Optional properties:
+
+- cpu-offset: For SMP, the offset to the per-cpu local timer
+ programming memory range, to be scaled by the sequential, zero-based
+ hardware cpu number.
+
+
+Example:
+
+timer@200 {
+ compatible = "jcore,pit";
+ reg = < 0x200 0x30 >;
+ cpu-offset = < 0x300 >;
+ interrupts = < 0x48 >;
+};