summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorRich Felker <dalias@libc.org>2016-05-17 23:18:09 +0000
committerRich Felker <dalias@libc.org>2016-06-08 21:54:12 +0000
commitb500f0991847cee6ef93453191784eeb064a9e42 (patch)
treeb2f775e34f123a8510acc8d9666140e77a26b724
parent708c930f013d859dfd100e222b24d3f1ab95cced (diff)
downloadlinux-sh-b500f0991847cee6ef93453191784eeb064a9e42.tar.gz
of: add J-Core cpu bindings
Signed-off-by: Rich Felker <dalias@libc.org>
-rw-r--r--Documentation/devicetree/bindings/jcore/cpus.txt49
1 files changed, 49 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/jcore/cpus.txt b/Documentation/devicetree/bindings/jcore/cpus.txt
new file mode 100644
index 000000000000..2da2dfcf45d5
--- /dev/null
+++ b/Documentation/devicetree/bindings/jcore/cpus.txt
@@ -0,0 +1,49 @@
+===================
+J-Core cpu bindings
+===================
+
+The J-Core processors are open source CPU cores that can be built as FPGA
+soft cores or ASICs. The device tree is also responsible for describing the
+cache controls and, for SMP configurations, all details of the SMP method.
+
+The current version of this document covers only uniprocessor configurations.
+
+
+---------------------
+Top-level "cpus" node
+---------------------
+
+Required properties:
+
+- #address-cells: Must be 1.
+
+- #size-cells: Must be 0.
+
+
+--------------------
+Individual cpu nodes
+--------------------
+
+Required properties:
+
+- device_type: Must be "cpu".
+
+- compatible: Must be "jcore,j2".
+
+- reg: The sequential, zero-based hardware cpu number. Must be 0 on
+ uniprocessor systems.
+
+Optional properties:
+
+- clock-frequency: Clock frequency of the cpu in Hz.
+
+
+---------------------
+Cache controller node
+---------------------
+
+Required properties:
+
+- compatible: Must be "jcore,cache".
+
+- reg: A memory range for the cache controller registers.