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authorPaul Burton <paul.burton@imgtec.com>2016-08-19 18:18:28 +0100
committerRalf Baechle <ralf@linux-mips.org>2016-09-29 18:59:49 +0200
commit67acd8d5c606cf42e6726767d705851dec9f6a34 (patch)
treef47a7004f00792f0c9c05590dda085bdfa2e1a72
parentebd0e0f503d0774407a63ebb5ec1a90bb54941f5 (diff)
downloadlinux-sh-67acd8d5c606cf42e6726767d705851dec9f6a34.tar.gz
MIPS: clear execution hazard after changing FTLB enable
On current P-series cores from Imagination the FTLB can be enabled or disabled via a bit in the Config6 register, and an execution hazard is created by changing the value of bit. The ftlb_disable function already cleared that hazard but that does no good for other callers. Clear the hazard in the set_ftlb_enable function that creates it, and only for the cores where it applies. This has the effect of reverting c982c6d6c48b ("MIPS: cpu-probe: Remove cp0 hazard barrier when enabling the FTLB") which was incorrect. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Fixes: c982c6d6c48b ("MIPS: cpu-probe: Remove cp0 hazard barrier when enabling the FTLB") Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14023/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
-rw-r--r--arch/mips/kernel/cpu-probe.c3
1 files changed, 1 insertions, 2 deletions
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 5069b5b1488f..dd3175442c9e 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -376,8 +376,6 @@ static int __init ftlb_disable(char *s)
return 1;
}
- back_to_back_c0_hazard();
-
config4 = read_c0_config4();
/* Check that FTLB has been disabled */
@@ -560,6 +558,7 @@ static int set_ftlb_enable(struct cpuinfo_mips *c, enum ftlb_flags flags)
}
write_c0_config6(config);
+ back_to_back_c0_hazard();
break;
case CPU_I6400:
/* There's no way to disable the FTLB */