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authorRich Felker <dalias@libc.org>2016-05-17 23:18:09 +0000
committerRich Felker <dalias@libc.org>2016-10-18 18:55:05 -0400
commit936900f00439c695a6c7d7d41b92c4421a2c75ef (patch)
treeed3e372ef90bf691870a9f6adf7648e3edfc0468
parentce4a6ae721a4c047983368d4a7c53600fe930e43 (diff)
downloadlinux-sh-936900f00439c695a6c7d7d41b92c4421a2c75ef.tar.gz
of: add J-Core cpu bindings
Signed-off-by: Rich Felker <dalias@libc.org>
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+===================
+J-Core cpu bindings
+===================
+
+The J-Core processors are open source CPU cores that can be built as FPGA
+soft cores or ASICs. The device tree is also responsible for describing the
+cache controls and, for SMP configurations, all details of the SMP method.
+
+The current version of this document covers only uniprocessor configurations.
+
+
+---------------------
+Top-level "cpus" node
+---------------------
+
+Required properties:
+
+- #address-cells: Must be 1.
+
+- #size-cells: Must be 0.
+
+
+--------------------
+Individual cpu nodes
+--------------------
+
+Required properties:
+
+- device_type: Must be "cpu".
+
+- compatible: Must be "jcore,j2".
+
+- reg: The sequential, zero-based hardware cpu number. Must be 0 on
+ uniprocessor systems.
+
+Optional properties:
+
+- clock-frequency: Clock frequency of the cpu in Hz.
+
+
+---------------------
+Cache controller node
+---------------------
+
+Required properties:
+
+- compatible: Must be "jcore,cache".
+
+- reg: A memory range for the cache controller registers.