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authorRich Felker <dalias@libc.org>2016-05-17 23:18:29 +0000
committerRich Felker <dalias@libc.org>2016-10-18 18:55:06 -0400
commitf6f2932ca31dd341e0da092f5a37dee6926938db (patch)
treed3052ed422dbac5e4b8d7ba21d430b272763bd52
parent936900f00439c695a6c7d7d41b92c4421a2c75ef (diff)
downloadlinux-sh-f6f2932ca31dd341e0da092f5a37dee6926938db.tar.gz
of: add J-Core interrupt controller bindings
Signed-off-by: Rich Felker <dalias@libc.org> Acked-by: Rob Herring <robh@kernel.org>
-rw-r--r--Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt26
1 files changed, 26 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt b/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt
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+++ b/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt
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+J-Core Advanced Interrupt Controller
+
+Required properties:
+
+- compatible: Should be "jcore,aic1" for the (obsolete) first-generation aic
+ with 8 interrupt lines with programmable priorities, or "jcore,aic2" for
+ the "aic2" core with 64 interrupts.
+
+- reg: Memory region(s) for configuration. For SMP, there should be one
+ region per cpu, indexed by the sequential, zero-based hardware cpu
+ number.
+
+- interrupt-controller: Identifies the node as an interrupt controller
+
+- #interrupt-cells: Specifies the number of cells needed to encode an
+ interrupt source. The value shall be 1.
+
+
+Example:
+
+aic: interrupt-controller@200 {
+ compatible = "jcore,aic2";
+ reg = < 0x200 0x30 0x500 0x30 >;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+};