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authorRich Felker <dalias@libc.org>2016-02-15 18:36:33 +0000
committerRich Felker <dalias@libc.org>2016-04-11 22:55:59 +0000
commit1a6c08fae60bdb8bfebf71ffd915aaca0b1247bc (patch)
tree772609751233662f6b9cb918d95bdc67095bd0ee
parent9f70cf81462fff62a8256485c4c8896f57b90540 (diff)
downloadlinux-sh-1a6c08fae60bdb8bfebf71ffd915aaca0b1247bc.tar.gz
sh: do not perform IPI-based cache flush except on boards that need it
Signed-off-by: Rich Felker <dalias@libc.org>
-rw-r--r--arch/sh/mm/cache.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/sh/mm/cache.c b/arch/sh/mm/cache.c
index bf56432a3a12..8d14af215c90 100644
--- a/arch/sh/mm/cache.c
+++ b/arch/sh/mm/cache.c
@@ -42,6 +42,8 @@ static inline void cacheop_on_each_cpu(void (*func) (void *info), void *info,
{
preempt_disable();
+ /* Needing IPI for cross-core flush is SHX3-specific. */
+#ifdef CONFIG_CPU_SHX3
/*
* It's possible that this gets called early on when IRQs are
* still disabled due to ioremapping by the boot CPU, so don't
@@ -49,6 +51,7 @@ static inline void cacheop_on_each_cpu(void (*func) (void *info), void *info,
*/
if (num_online_cpus() > 1)
smp_call_function(func, info, wait);
+#endif
func(info);