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authorRich Felker <dalias@libc.org>2016-05-17 23:18:58 +0000
committerRich Felker <dalias@libc.org>2016-10-18 18:55:07 -0400
commit353982a7ebda3d4f49381662e0402755eda0d4eb (patch)
tree2607e449669601aa00a106362103aa426b397d26
parentcb8c66facea1a460b20b5c5796c5ab38eee0da48 (diff)
downloadlinux-sh-353982a7ebda3d4f49381662e0402755eda0d4eb.tar.gz
of: add J-Core timer bindings
Signed-off-by: Rich Felker <dalias@libc.org> Acked-by: Rob Herring <robh@kernel.org>
-rw-r--r--Documentation/devicetree/bindings/timer/jcore,pit.txt24
1 files changed, 24 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/timer/jcore,pit.txt b/Documentation/devicetree/bindings/timer/jcore,pit.txt
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+J-Core Programmable Interval Timer and Clocksource
+
+Required properties:
+
+- compatible: Must be "jcore,pit".
+
+- reg: Memory region(s) for timer/clocksource registers. For SMP,
+ there should be one region per cpu, indexed by the sequential,
+ zero-based hardware cpu number.
+
+- interrupts: An interrupt to assign for the timer. The actual pit
+ core is integrated with the aic and allows the timer interrupt
+ assignment to be programmed by software, but this property is
+ required in order to reserve an interrupt number that doesn't
+ conflict with other devices.
+
+
+Example:
+
+timer@200 {
+ compatible = "jcore,pit";
+ reg = < 0x200 0x30 0x500 0x30 >;
+ interrupts = < 0x48 >;
+};