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2016-10-13irqchip/jcore: revert to safer fix for percpu irqsjcore-4.6-20161013jcore-4.6Rich Felker-10/+19
Signed-off-by: Rich Felker <dalias@libc.org>
2016-10-10irqchip/jcore: fix lost per-cpu interruptsjcore-4.6-20161010Rich Felker-1/+10
The J-Core AIC does not have separate interrupt numbers reserved for cpu-local vs global interrupts. Instead, the driver requesting the irq is expected to know whether its device uses per-cpu interrupts or not. Previously it was assumed that handle_simple_irq could work for both cases, but it intentionally drops interrupts for an irq number that already has a handler running. This resulted in the timer interrupt for one cpu being lost when multiple cpus' timers were set for approximately the same expiration time, leading to stalls. In theory the same could also happen with IPIs. One possible solution would be to use a wrapper handler function which determines at irq time whether the irq being handled was registered as percpu or not, and dispatches it to either handle_simple_irq or handle_percpu_irq. However handle_simple_irq is unnecessarily expensive for hardware that always delivers interrupts on a fixed cpu, and the runtime branch also has a small but nonzero cost. Instead, use handle_percpu_irq for all irqs. Signed-off-by: Rich Felker <dalias@libc.org>
2016-08-10mmc: revert 4d9135a: mmc: disable rescan for card changejcore-4.6-20160810Rich Felker-3/+2
Fix of the underlying bug makes this hack no longer necessary. Signed-off-by: Rich Felker <dalias@libc.org>
2016-08-10timer/jcore: backport changes sent upstream for 4.8Rich Felker-137/+108
Signed-off-by: Rich Felker <dalias@libc.org>
2016-08-10spi/jcore: backport changes sent upstream for 4.8Rich Felker-54/+71
Signed-off-by: Rich Felker <dalias@libc.org>
2016-08-10irqchip/jcore: backport changes sent upstream for 4.8Rich Felker-48/+47
Signed-off-by: Rich Felker <dalias@libc.org>
2016-08-10spi: Split bus and I/O lockingMark Brown-21/+23
The current SPI code attempts to use bus_lock_mutex for two purposes. One is to implement spi_bus_lock() which grants exclusive access to the bus. The other is to serialize access to the physical hardware. This duplicate purpose causes confusion which leads to cases where access is not locked when a caller holds the bus lock mutex. Fix this by splitting out the I/O functionality into a new io_mutex. This means taking both mutexes in the DMA path, replacing the existing mutex with the new I/O one in the message pump (the mutex now always being taken in the message pump) and taking the bus lock mutex in spi_sync(), allowing __spi_sync() to have no mutex handling. While we're at it hoist the mutex further up the message pump before we power up the device so that all power up/down of the block is covered by it and there are no races with in-line pumping of messages. Reported-by: Rich Felker <dalias@libc.org> Tested-by: Rich Felker <dalias@libc.org> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-08-10spi: Add DMA support for spi_flash_read()Vignesh R-0/+32
Few SPI devices provide accelerated read interfaces to read from SPI-NOR flash devices. These hardwares also support DMA to transfer data from flash to memory either via mem-to-mem DMA or dedicated slave DMA channels. Hence, add support for DMA in order to improve throughput and reduce CPU load. Use spi_map_buf() to get sg table for the buffer and pass it to SPI driver. Signed-off-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2016-08-10sh: use common clock framework with device tree boardsRich Felker-0/+5
Enable common clk framework for DT-based boards and disable code that depends on the legacy sh clk framework when common clk is enabled. Once legacy drivers are converted over, the old code can be removed entirely. Signed-off-by: Rich Felker <dalias@libc.org>
2016-07-15uio: allow use on nommu systemsRich Felker-1/+0
mmap of uio devices does not seem to work without further nommu-specific support, but interrupt handling already works, and userspace drivers for nommu systems can simply use physical mmio addresses from userspace directly anyway without mmap. Signed-off-by: Rich Felker <dalias@libc.org>
2016-06-21sh: add AF_PACKET socket support to j2 defconfigjcore-4.6-20160620Rich Felker-0/+1
2016-06-08sh: add smp support to j2 defconfigjcore-4.6-20160608Rich Felker-0/+1
2016-06-08sh: add jcore emac support to j2 defconfigRich Felker-0/+1
2016-06-08mmc: disable rescan for card changeRich Felker-2/+3
This is a hack to fix a nasty bug: the rescan is completely unsynchronized with use of the spi bus for spi-based mmc, and thus clobbers in-progress transfers when it happens. No idea what the right fix is.
2016-06-08jcore sched_clockRich Felker-0/+11
2016-06-08ethernet/jcore_emac: add J-Core ethernet driverRich Felker-0/+1549
This is sloppy and not ready for upstream.
2016-06-08sh: do not perform IPI-based cache flush except on boards that need itRich Felker-0/+3
Signed-off-by: Rich Felker <dalias@libc.org>
2016-06-08sh: add SMP support for J2Rich Felker-0/+144
Signed-off-by: Rich Felker <dalias@libc.org>
2016-06-08sh: SMP support for SH2 entry.SRich Felker-0/+50
The SH2 version of entry.S uses global variables, which need to be cpu-local in order to work with SMP. For ease of access from asm, simply use arrays indexed by cpu number, and require the availability of an address (mmio register or properly setup per-cpu memory) from which the current cpu's index can be read. Signed-off-by: Rich Felker <dalias@libc.org>
2016-06-08sh: add working futex atomic ops on userspace addresses for smpRich Felker-124/+134
The version of futex.h in asm-generic should really be adapted to do the same thing so that this hideous code does not have to be duplicated per-arch. Signed-off-by: Rich Felker <dalias@libc.org>
2016-06-08sh: add J2 atomics using the cas.l instructionRich Felker-210/+469
Signed-off-by: Rich Felker <dalias@libc.org>
2016-06-08spi: add driver for J-Core SPI controllerRich Felker-0/+220
The J-Core "spi2" device is a PIO-based SPI master controller. It differs from "bitbang" devices in that that it's clocked in hardware rather than via soft clock modulation over gpio, and performs byte-at-a-time transfers between the cpu and SPI controller. This driver will be extended to support future versions of the J-Core SPI controller with DMA transfers when they become available. Signed-off-by: Rich Felker <dalias@libc.org>
2016-06-08sh: add device tree source for J2 FPGA on Mimas v2 boardRich Felker-0/+91
Signed-off-by: Rich Felker <dalias@libc.org>
2016-06-08sh: add defconfig for J-Core J2Rich Felker-0/+38
This defconfig is intended not to be specific to a particular board; it enables drivers for all currently-supported hardware, and should be updated to include additional drivers as they are added. Signed-off-by: Rich Felker <dalias@libc.org>
2016-06-08clocksource: add J-Core timer/clocksource driverRich Felker-0/+291
At the hardware level, the J-Core PIT is integrated with the interrupt controller, but it is represented as its own device and has an independent programming interface. It provides a 12-bit countdown timer, which is not presently used, and a periodic timer. The interval length for the latter is programmable via a 32-bit throttle register whose units are determined by a bus-period register. The periodic timer is used to implement both periodic and oneshot clock event modes; in oneshot mode the interrupt handler simply disables the timer as soon as it fires. Despite its device tree node representing an interrupt for the PIT, the actual irq generated is programmable, not hard-wired. The driver is responsible for programming the PIT to generate the hardware irq number that the DT assigns to it. On SMP configurations, J-Core provides cpu-local instances of the PIT; no broadcast timer is needed. This driver supports the creation of the necessary per-cpu clock_event_device instances. The code has been tested and works on SMP, but will not be usable without additional J-Core SMP-support patches and appropriate hardware capable of running SMP. A nanosecond-resolution clocksource is provided using the J-Core "RTC" registers, which give a 64-bit seconds count and 32-bit nanoseconds. The driver converts these to a 64-bit nanoseconds count. Signed-off-by: Rich Felker <dalias@libc.org>
2016-06-08irqchip: add J-Core AIC driverRich Felker-0/+102
There are two versions of the J-Core interrupt controller in use, aic1 which generates interrupts with programmable priorities, but only supports 8 irq lines and maps them to cpu traps in the range 17 to 24, and aic2 which uses traps in the range 64-127 and supports up to 128 irqs, with priorities dependent on the interrupt number. The Linux driver does not make use of priorities anyway. For simplicity, there is no aic1-specific logic in the driver beyond setting the priority register, which is necessary for interrupts to work at all. Eventually aic1 will likely be phased out, but it's currently in use in deployments and all released bitstream binaries. Signed-off-by: Rich Felker <dalias@libc.org>
2016-06-08sh: add AT_HWCAP flag for J-Core cas.l instructionRich Felker-0/+3
Signed-off-by: Rich Felker <dalias@libc.org>
2016-06-08sh: add support for J-Core J2 processorRich Felker-5/+117
At the CPU/ISA level, the J2 is compatible with SH-2, and thus the changes to add J2 support build on existing SH-2 support. However, J2 does not duplicate the memory-mapped SH-2 features like the cache interface. Instead, the cache interfaces is described in the device tree, and new code is added to be able to access the flat device tree at early boot before it is unflattened. Support is also added for receiving interrupts on trap numbers in the range 16 to 31, since the J-Core aic1 interrupt controller generates these traps. This range was unused but nominally for hardware exceptions on SH-2, and a few values in this range were used for exceptions on SH-2A, but SH-2A has its own version of the relevant code. No individual cpu subtypes are added for J2 since the intent moving forward is to represent SoCs with device tree rather than as hard-coded subtypes in the kernel. The CPU_SUBTYPE_J2 Kconfig item exists only to fit into the existing cpu selection mechanism until it is overhauled. Signed-off-by: Rich Felker <dalias@libc.org>
2016-06-08of: add J-Core SPI master bindingsRich Felker-0/+23
Signed-off-by: Rich Felker <dalias@libc.org> Acked-by: Rob Herring <robh@kernel.org>
2016-06-08of: add J-Core timer bindingsRich Felker-0/+29
Signed-off-by: Rich Felker <dalias@libc.org>
2016-06-08of: add J-Core interrupt controller bindingsRich Felker-0/+30
Signed-off-by: Rich Felker <dalias@libc.org>
2016-06-08of: add J-Core cpu bindingsRich Felker-0/+49
Signed-off-by: Rich Felker <dalias@libc.org>
2016-06-08of: add vendor prefix for J-CoreRich Felker-0/+1
The J-Core project (j-core.org) produces open source cpu and SoC peripheral cores synthesizable as FPGA bitstreams or ASICs. Signed-off-by: Rich Felker <dalias@libc.org> Acked-by: Rob Herring <robh@kernel.org>
2016-06-08futex: fix shared futex operations on nommuRich Felker-0/+2
The shared get_futex_key code does not work on nommu, but is not needed anyway because it's impossible for a given backing to have multiple distinct virtual addresses on nommu. Simply disable these code paths by refraining from setting FLAG_SHARED when CONFIG_MMU is not enabled. Signed-off-by: Rich Felker <dalias@libc.org>
2016-06-08sh: fix build regression with CONFIG_OF && !CONFIG_OF_FLATTREERich Felker-4/+4
Such a configuration could only be selected by manually selecting CONFIG_OF; SH_DEVICE_TREE selects both. The affected code is using the flat DTB at boot time and thus rightfully should depend on OF_FLATTREE, not just OF. Signed-off-by: Rich Felker <dalias@libc.org>
2016-06-08sh: allow clocksource drivers to register sched_clock backendsRich Felker-0/+1
There is no arch-specific sched_clock implementation for sh, resulting in use of the old default jiffies-based implementation. Instead, use the modern generic sched_clock framework so that drivers can register better backends. Signed-off-by: Rich Felker <dalias@libc.org>
2016-06-08sh: make heartbeat driver explicitly non-modularPaul Gortmaker-29/+3
The Kconfig for this driver is currently: config HEARTBEAT bool "Heartbeat LED" ....meaning that it currently is not being built as a module by anyone. Lets remove the modular code that is essentially orphaned, so that when reading the driver there is no doubt it is builtin-only. Since module_init translates to device_initcall in the non-modular case, the init ordering remains unchanged with this commit. We explicitly disallow a driver unbind, since that doesn't have a sensible use case anyway, and it allows us to drop the ".remove" code for non-modular drivers. We also delete the MODULE_LICENSE tag etc. since all that information is already contained at the top of the file in the comments. Cc: Yoshinori Sato <ysato@users.sourceforge.jp> Cc: Rich Felker <dalias@libc.org> Cc: linux-sh@vger.kernel.org Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Rich Felker <dalias@libc.org>
2016-06-08sh: make board-secureedge5410 explicitly non-modularPaul Gortmaker-2/+1
The Kconfig currently controlling compilation of this code is: config SH_SECUREEDGE5410 bool "SecureEdge5410" ....meaning that it currently is not being built as a module by anyone. Lets remove the couple traces of modularity so that when reading the driver there is no doubt it is builtin-only. Since module_init translates to device_initcall in the non-modular case, the init ordering remains unchanged with this commit. We don't replace module.h with init.h since the file already has that. Cc: Yoshinori Sato <ysato@users.sourceforge.jp> Cc: Rich Felker <dalias@libc.org> Cc: linux-sh@vger.kernel.org Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Rich Felker <dalias@libc.org>
2016-06-08sh: make mm/asids-debugfs explicitly non-modularPaul Gortmaker-4/+1
The Makefile/Kconfig currently controlling compilation of this code is: obj-$(CONFIG_DEBUG_FS) += $(debugfs-y) debugfs-y := asids-debugfs.o lib/Kconfig.debug:config DEBUG_FS lib/Kconfig.debug: bool "Debug Filesystem" ....meaning that it currently is not being built as a module by anyone. Lets remove the couple traces of modular code, so that when reading the driver there is no doubt it is builtin-only. Since module_init translates to device_initcall in the non-modular case, the init ordering remains unchanged with this commit. Cc: Yoshinori Sato <ysato@users.sourceforge.jp> Cc: Rich Felker <dalias@libc.org> Cc: linux-sh@vger.kernel.org Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Rich Felker <dalias@libc.org>
2016-06-08sh: make time.c explicitly non-modularPaul Gortmaker-2/+1
The Makefile currently controlling compilation of this code is: obj-y := debugtraps.o dma-nommu.o dumpstack.o \ [...] syscalls_$(BITS).o time.o topology.o traps.o \ traps_$(BITS).o unwinder.o ....meaning that it currently is not being built as a module by anyone. Lets remove the couple traces of modular code, so that when reading the driver there is no doubt it is builtin-only. Since module_init translates to device_initcall in the non-modular case, the init ordering remains unchanged with this commit. Cc: Yoshinori Sato <ysato@users.sourceforge.jp> Cc: Rich Felker <dalias@libc.org> Cc: Paul Gortmaker <paul.gortmaker@windriver.com> Cc: linux-sh@vger.kernel.org Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Rich Felker <dalias@libc.org>
2016-06-08sh: fix futex/robust_list on nommu modelsRich Felker-0/+1
The futex cmpxchg runtime testing in kernel/futex.c depends on accesses to address 0 producing EFAULT, which obviously does not work on nommu. Since SH always has cmpxchg, disable the broken runtime detection. At some point this should be fixed at the kernel/futex.c level. UP machines can always provide a working cmpxchg with interrupt masking, and SMP cannot function without a working cmpxchg anyway. Signed-off-by: Rich Felker <dalias@libc.org>
2016-06-08sh: disable aliased page logic on NOMMU modelsRich Felker-0/+8
SH3/4 (with MMU) have a virtually indexed cache, requiring explicit work to avoid consistency problems arising from having the same physical address range cached in multiple cache lines. This is unneeded for the NOMMU case, and some of the resulting code paths (kmap_coherent) don't work. SH2 only avoided this problem by having a 4-way associative cache with way size equal to the page size (4k), yielding no cache index bits outside of the page offset and thus no aliases. Signed-off-by: Rich Felker <dalias@libc.org>
2016-06-08sh: make sigcontext definition consistent across fpu/nofpu modelsRich Felker-3/+0
Up until now, the SH version of the sigcontext structure, and thus mcontext_t/ucontext_t, varied depending on the cpu model the kernel was built to run on. SH-4 (including SH-4A) and SH-2A used the form with space for FPU registers, and everything else used a form that omitted them. From a userspace perspective, however, the structure layout must be fixed for a given ABI. Traditionally glibc and uClibc used the form with space for FPU registers only when __SH4__ (which implies FPU; __SH4_NOFPU__ is the predefined macro for SH-4 but with no-FPU ABI) was defined. As a result: - SH-4 no-FPU programs never matched kernel sigcontext. - SH-3 programs did not match kernel sigcontext if run on SH-4, despite an apparent intent that they be compatible. - SH-2 and SH-2A programs (using uClibc) did not match kernel sigcontext if run on SH-2A. The mismatch might seem inconsequential because it occurs at the end of the sigcontext structure, but sigcontext is embedded as uc_mcontext in ucontext_t, where it is followed by uc_sigmask, an important member for signal handlers to have access to. In particular, access to uc_sigmask is necessary for a correct implementation of thread cancellation. It would be possible to retain support for both sigcontext ABIs via a personality mechanism, but since many configurations were already broken and nobody noticed, and since there are very few if any users of legacy no-FPU models anymore, I have opted to just remove the variation and always include space for the FPU registers in sigcontext. This was proposed and discussed on a thread "SH sigcontext ABI is broken" cross-posted to linux-sh, libc-alpha, and musl libc lists in June 2015, and no objections were raised. Signed-off-by: Rich Felker <dalias@libc.org>
2016-06-08sh: add support for linking a builtin device tree blob in the kernelRich Felker-3/+41
Signed-off-by: Rich Felker <dalias@libc.org>
2016-06-08sh: cmpxchg: fix a bit shift bug in big_endian osPan Xinhui-1/+1
Correct bitoff in big endian OS. Current code works correctly for 1 byte but not for 2 bytes. Fixes: 3226aad81aa6 ("sh: support 1 and 2 byte xchg") Signed-off-by: Pan Xinhui <xinhui.pan@linux.vnet.ibm.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Rich Felker <dalias@libc.org>
2016-06-08tmpfs/ramfs: fix VM_MAYSHARE mappings for NOMMURich Felker-6/+2
The nommu do_mmap expects f_op->get_unmapped_area to either succeed or return -ENOSYS for VM_MAYSHARE (e.g. private read-only) mappings. Returning addr in the non-MAP_SHARED case was completely wrong, and only happened to work because addr was 0. However, it prevented VM_MAYSHARE mappings from sharing backing with the fs cache, and forced such mappings (including shareable program text) to be copied whenever the number of mappings transitioned from 0 to 1, impacting performance and memory usage. Subsequent mappings beyond the first still correctly shared memory with the first. Instead, treat VM_MAYSHARE identically to VM_SHARED at the file ops level; do_mmap already handles the semantic differences between them. Signed-off-by: Rich Felker <dalias@libc.org> Cc: Michal Hocko <mhocko@suse.com> Cc: Greg Ungerer <gerg@uclinux.org> Cc: Geert Uytterhoeven <geert@linux-m68k.org> Cc: Yoshinori Sato <ysato@users.sourceforge.jp> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2016-05-15Linux 4.6v4.6Linus Torvalds-1/+1
2016-05-15Merge branch 'x86-urgent-for-linus' of ↵Linus Torvalds-2/+2
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull x86 fix from Thomas Gleixner: "Just the missing compat entry for the new pread/writev2" * 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86: Use compat version for preadv2 and pwritev2
2016-05-14Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/netLinus Torvalds-45/+175
Pull networking fixes from David Miller: 1) Fix mvneta/bm dependencies, from Arnd Bergmann. 2) RX completion hw bug workaround in bnxt_en, from Michael Chan. 3) Kernel pointer leak in nf_conntrack, from Linus. 4) Hoplimit route attribute limits not enforced properly, from Paolo Abeni. 5) qlcnic driver NULL deref fix from Dan Carpenter. * git://git.kernel.org/pub/scm/linux/kernel/git/davem/net: arm64: bpf: jit JMP_JSET_{X,K} net/route: enforce hoplimit max value nf_conntrack: avoid kernel pointer value leak in slab name drivers: net: xgene: fix register offset drivers: net: xgene: fix statistics counters race condition drivers: net: xgene: fix ununiform latency across queues drivers: net: xgene: fix sharing of irqs drivers: net: xgene: fix IPv4 forward crash xen-netback: fix extra_info handling in xenvif_tx_err() net: mvneta: bm: fix dependencies again bnxt_en: Add workaround to detect bad opaque in rx completion (part 2) bnxt_en: Add workaround to detect bad opaque in rx completion (part 1) qlcnic: potential NULL dereference in qlcnic_83xx_get_minidump_template()
2016-05-14arm64: bpf: jit JMP_JSET_{X,K}Zi Shen Lim-0/+1
Original implementation commit e54bcde3d69d ("arm64: eBPF JIT compiler") had the relevant code paths, but due to an oversight always fail jiting. As a result, we had been falling back to BPF interpreter whenever a BPF program has JMP_JSET_{X,K} instructions. With this fix, we confirm that the corresponding tests in lib/test_bpf continue to pass, and also jited. ... [ 2.784553] test_bpf: #30 JSET jited:1 188 192 197 PASS [ 2.791373] test_bpf: #31 tcpdump port 22 jited:1 325 677 625 PASS [ 2.808800] test_bpf: #32 tcpdump complex jited:1 323 731 991 PASS ... [ 3.190759] test_bpf: #237 JMP_JSET_K: if (0x3 & 0x2) return 1 jited:1 110 PASS [ 3.192524] test_bpf: #238 JMP_JSET_K: if (0x3 & 0xffffffff) return 1 jited:1 98 PASS [ 3.211014] test_bpf: #249 JMP_JSET_X: if (0x3 & 0x2) return 1 jited:1 120 PASS [ 3.212973] test_bpf: #250 JMP_JSET_X: if (0x3 & 0xffffffff) return 1 jited:1 89 PASS ... Fixes: e54bcde3d69d ("arm64: eBPF JIT compiler") Signed-off-by: Zi Shen Lim <zlim.lnx@gmail.com> Acked-by: Will Deacon <will.deacon@arm.com> Acked-by: Yang Shi <yang.shi@linaro.org> Signed-off-by: David S. Miller <davem@davemloft.net>