From 200d15479c0bc48471ee7b8e538ce33af990f82e Mon Sep 17 00:00:00 2001 From: Stefan Kristiansson Date: Thu, 17 Jul 2014 22:09:10 +0300 Subject: add or1k (OpenRISC 1000) architecture port With the exception of a fenv implementation, the port is fully featured. The port has been tested in or1ksim, the golden reference functional simulator for OpenRISC 1000. It passes all libc-test tests (except the math tests that requires a fenv implementation). The port assumes an or1k implementation that has support for atomic instructions (l.lwa/l.swa). Although it passes all the libc-test tests, the port is still in an experimental state, and has yet experienced very little 'real-world' use. --- crt/or1k/crti.s | 11 +++++++++++ crt/or1k/crtn.s | 9 +++++++++ 2 files changed, 20 insertions(+) create mode 100644 crt/or1k/crti.s create mode 100644 crt/or1k/crtn.s (limited to 'crt') diff --git a/crt/or1k/crti.s b/crt/or1k/crti.s new file mode 100644 index 00000000..7e741459 --- /dev/null +++ b/crt/or1k/crti.s @@ -0,0 +1,11 @@ +.section .init +.global _init +_init: + l.addi r1,r1,-4 + l.sw 0(r1),r9 + +.section .fini +.global _fini +_fini: + l.addi r1,r1,-4 + l.sw 0(r1),r9 diff --git a/crt/or1k/crtn.s b/crt/or1k/crtn.s new file mode 100644 index 00000000..4185a027 --- /dev/null +++ b/crt/or1k/crtn.s @@ -0,0 +1,9 @@ +.section .init + l.lwz r9,0(r1) + l.jr r9 + l.addi r1,r1,4 + +.section .fini + l.lwz r9,0(r1) + l.jr r9 + l.addi r1,r1,4 -- cgit v1.2.1