From 0a48860c27a8eb291bcc7616ea9eb073dc660cab Mon Sep 17 00:00:00 2001 From: Rich Felker Date: Fri, 24 May 2019 10:46:08 -0400 Subject: add riscv64 architecture support Author: Alex Suykov Author: Aric Belsito Author: Drew DeVault Author: Michael Clark Author: Michael Forney Author: Stefan O'Rear This port has involved the work of many people over several years. I have tried to ensure that everyone with substantial contributions has been credited above; if any omissions are found they will be noted later in an update to the authors/contributors list in the COPYRIGHT file. The version committed here comes from the riscv/riscv-musl repo's commit 3fe7e2c75df78eef42dcdc352a55757729f451e2, with minor changes by me for issues found during final review: - a_ll/a_sc atomics are removed (according to the ISA spec, lr/sc are not safe to use in separate inline asm fragments) - a_cas[_p] is fixed to be a memory barrier - the call from the _start assembly into the C part of crt1/ldso is changed to allow for the possibility that the linker does not place them nearby each other. - DTP_OFFSET is defined correctly so that local-dynamic TLS works - reloc.h LDSO_ARCH logic is simplified and made explicit. - unused, non-functional crti/n asm files are removed. - an empty .sdata section is added to crt1 so that the __global_pointer reference is resolvable. - indentation style errors in some asm files are fixed. --- src/math/riscv64/fminf.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) create mode 100644 src/math/riscv64/fminf.c (limited to 'src/math/riscv64/fminf.c') diff --git a/src/math/riscv64/fminf.c b/src/math/riscv64/fminf.c new file mode 100644 index 00000000..32156e80 --- /dev/null +++ b/src/math/riscv64/fminf.c @@ -0,0 +1,15 @@ +#include + +#if __riscv_flen >= 32 + +float fminf(float x, float y) +{ + __asm__ ("fmin.s %0, %1, %2" : "=f"(x) : "f"(x), "f"(y)); + return x; +} + +#else + +#include "../fminf.c" + +#endif -- cgit v1.2.1