summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorRich Felker <dalias@libc.org>2016-07-22 15:14:30 +0000
committerRich Felker <dalias@libc.org>2016-07-22 15:14:30 +0000
commit83fa6a3f572a634017371795bfb045e766cf0ca1 (patch)
tree95e4f5997c538b4567c2732faf8b2cdd8b6ee697
parent4bf9caf1cc7cb4eb225dcd96f8bd42ac10d72e53 (diff)
downloadlinux-sh-83fa6a3f572a634017371795bfb045e766cf0ca1.tar.gz
pit binding updates
-rw-r--r--Documentation/devicetree/bindings/timer/jcore,pit.txt14
1 files changed, 5 insertions, 9 deletions
diff --git a/Documentation/devicetree/bindings/timer/jcore,pit.txt b/Documentation/devicetree/bindings/timer/jcore,pit.txt
index ebb0b2d70dc4..0f42af447dea 100644
--- a/Documentation/devicetree/bindings/timer/jcore,pit.txt
+++ b/Documentation/devicetree/bindings/timer/jcore,pit.txt
@@ -4,7 +4,10 @@ Required properties:
- compatible: Must be "jcore,pit".
-- reg: Memory region for timer/clocksource registers.
+- reg: Memory region(s) for timer/clocksource registers. For SMP,
+ there should be one region per cpu, indexed by the sequential,
+ zero-based hardware cpu number (which is also the logical cpu
+ number).
- interrupts: An interrupt to assign for the timer. The actual pit
core is integrated with the aic and allows the timer interrupt
@@ -12,18 +15,11 @@ Required properties:
required in order to reserve an interrupt number that doesn't
conflict with other devices.
-Optional properties:
-
-- cpu-offset: For SMP, the offset to the per-cpu local timer
- programming memory range, to be scaled by the sequential, zero-based
- hardware cpu number.
-
Example:
timer@200 {
compatible = "jcore,pit";
- reg = < 0x200 0x30 >;
- cpu-offset = < 0x300 >;
+ reg = < 0x200 0x30 0x500 0x30 >;
interrupts = < 0x48 >;
};