|author||Rich Felker <firstname.lastname@example.org>||2016-07-22 15:14:30 +0000|
|committer||Rich Felker <email@example.com>||2016-07-22 15:14:30 +0000|
pit binding updates
1 files changed, 5 insertions, 9 deletions
diff --git a/Documentation/devicetree/bindings/timer/jcore,pit.txt b/Documentation/devicetree/bindings/timer/jcore,pit.txt
index ebb0b2d70dc4..0f42af447dea 100644
@@ -4,7 +4,10 @@ Required properties:
- compatible: Must be "jcore,pit".
-- reg: Memory region for timer/clocksource registers.
+- reg: Memory region(s) for timer/clocksource registers. For SMP,
+ there should be one region per cpu, indexed by the sequential,
+ zero-based hardware cpu number (which is also the logical cpu
- interrupts: An interrupt to assign for the timer. The actual pit
core is integrated with the aic and allows the timer interrupt
@@ -12,18 +15,11 @@ Required properties:
required in order to reserve an interrupt number that doesn't
conflict with other devices.
-- cpu-offset: For SMP, the offset to the per-cpu local timer
- programming memory range, to be scaled by the sequential, zero-based
- hardware cpu number.
compatible = "jcore,pit";
- reg = < 0x200 0x30 >;
- cpu-offset = < 0x300 >;
+ reg = < 0x200 0x30 0x500 0x30 >;
interrupts = < 0x48 >;