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authorRich Felker <dalias@libc.org>2016-07-22 15:14:07 +0000
committerRich Felker <dalias@libc.org>2016-07-22 15:14:07 +0000
commitaebbc8cc82b665dc7b7a89ee777662eb7fe9dd3e (patch)
tree5e3c59efe9df72b249e233099ca1e755bde739a9
parentc8149cb2fe6819b0746818e9481e8abc77796129 (diff)
downloadlinux-sh-aebbc8cc82b665dc7b7a89ee777662eb7fe9dd3e.tar.gz
aic binding updates
-rw-r--r--Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt12
1 files changed, 4 insertions, 8 deletions
diff --git a/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt b/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt
index f52bb823eda7..b7a56ad2c041 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt
@@ -6,25 +6,21 @@ Required properties:
with 8 interrupt lines with programmable priorities, or "jcore,aic2" for
the "aic2" core with 64 interrupts.
-- reg: Memory region for configuration.
+- reg: Memory region(s) for configuration. For SMP, there should be one
+ region per cpu, indexed by the sequential, zero-based hardware cpu
+ number (which is also the logical cpu number).
- interrupt-controller: Identifies the node as an interrupt controller
- #interrupt-cells: Specifies the number of cells needed to encode an
interrupt source. The value shall be 1.
-Optional properties:
-
-- cpu-offset: For SMP, the offset to the per-cpu memory region for
- configuration, to be scaled by the sequential, zero-based hardware cpu
- number.
-
Example:
aic: interrupt-controller@200 {
compatible = "jcore,aic2";
- reg = < 0x200 0x10 >;
+ reg = < 0x200 0x30 0x500 0x30 >;
interrupt-controller;
#interrupt-cells = <1>;
};