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authorRich Felker <dalias@libc.org>2016-05-17 23:18:29 +0000
committerRich Felker <dalias@libc.org>2016-07-15 03:47:35 +0000
commitdf222a271a49d3025dca04af4ccc35e4645b6b15 (patch)
treee9ce4734bfc7e29f1a662c364ca7941966a1c67d
parentbe2e5dc29600f8727dcb548a6d0131d420bb43b0 (diff)
downloadlinux-sh-df222a271a49d3025dca04af4ccc35e4645b6b15.tar.gz
of: add J-Core interrupt controller bindings
Signed-off-by: Rich Felker <dalias@libc.org>
-rw-r--r--Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt30
1 files changed, 30 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt b/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt
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+++ b/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt
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+J-Core Advanced Interrupt Controller
+
+Required properties:
+
+- compatible: Should be "jcore,aic1" for the (obsolete) first-generation aic
+ with 8 interrupt lines with programmable priorities, or "jcore,aic2" for
+ the "aic2" core with 64 interrupts.
+
+- reg: Memory region for configuration.
+
+- interrupt-controller: Identifies the node as an interrupt controller
+
+- #interrupt-cells: Specifies the number of cells needed to encode an
+ interrupt source. The value shall be 1.
+
+Optional properties:
+
+- cpu-offset: For SMP, the offset to the per-cpu memory region for
+ configuration, to be scaled by the sequential, zero-based hardware cpu
+ number.
+
+
+Example:
+
+aic: interrupt-controller@200 {
+ compatible = "jcore,aic2";
+ reg = < 0x200 0x10 >;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+};