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authorRich Felker <dalias@libc.org>2016-05-17 23:18:58 +0000
committerRich Felker <dalias@libc.org>2016-06-08 00:35:37 +0000
commit59f31d5a61d7e12962e1db9145dced632fd3cb74 (patch)
treec9217f4099606a2b296e1b190fc71b6b3b683ce2
parentc094f85af29eadb63a2defe94a2360dce7f318ec (diff)
downloadlinux-sh-59f31d5a61d7e12962e1db9145dced632fd3cb74.tar.gz
of: add J-Core timer bindings
Signed-off-by: Rich Felker <dalias@libc.org>
-rw-r--r--Documentation/devicetree/bindings/timer/jcore,pit.txt29
1 files changed, 29 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/timer/jcore,pit.txt b/Documentation/devicetree/bindings/timer/jcore,pit.txt
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+J-Core Programmable Interval Timer and Clocksource
+
+Required properties:
+
+- compatible: Must be "jcore,pit".
+
+- reg: Memory region for timer/clocksource registers.
+
+- interrupts: An interrupt to assign for the timer. The actual pit
+ core is integrated with the aic and allows the timer interrupt
+ assignment to be programmed by software, but this property is
+ required in order to reserve an interrupt number that doesn't
+ conflict with other devices.
+
+Optional properties:
+
+- cpu-offset: For SMP, the offset to the per-cpu local timer
+ programming memory range, to be scaled by the sequential, zero-based
+ hardware cpu number.
+
+
+Example:
+
+timer@200 {
+ compatible = "jcore,pit";
+ reg = < 0x200 0x30 >;
+ cpu-offset = < 0x300 >;
+ interrupts = < 0x48 >;
+};