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authorHaojian Zhuang <haojian.zhuang@linaro.org>2014-05-11 16:05:58 +0800
committerJason Cooper <jason@lakedaemon.net>2014-05-19 00:35:23 +0000
commitb8802f76fe473d91886220498aeda157c492f2d1 (patch)
tree577ce870c39992ca6638ee3d3c0d66548a57db61 /Documentation/devicetree/bindings/arm/armada-370-xp-mpic.txt
parentc9eaa447e77efe77b7fa4c953bd62de8297fd6c5 (diff)
downloadlinux-sh-b8802f76fe473d91886220498aeda157c492f2d1.tar.gz
irqchip: gic: Use mask field in GICC_IAR
Bit[9:0] is interrupt ID field in GICC_IAR. Bit[12:10] is CPU ID field, and others are reserved. So we should use GICC_IAR_INT_ID_MASK to get interrupt ID. It's not a good way to use ~0x1c00 (CPU ID field) to get interrupt ID. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Link: https://lkml.kernel.org/r/1399795571-17231-3-git-send-email-haojian.zhuang@linaro.org Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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