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authorGregory CLEMENT <gregory.clement@free-electrons.com>2012-08-02 11:19:12 +0300
committerGregory CLEMENT <gregory.clement@free-electrons.com>2012-11-21 16:49:37 +0100
commit344e873e5657e8dc0631e4d1d42b69f7d625b02c (patch)
tree3df34d2662770a3b65d91911240acb87453bef2c /Documentation
parent7444dad2409afd94c08875e961ca61c5999cd606 (diff)
downloadlinux-sh-344e873e5657e8dc0631e4d1d42b69f7d625b02c.tar.gz
arm: mvebu: Add IPI support via doorbells
This patch enhances the IRQ controller driver to add support for Inter-Processor-Interrupts that are needed to enable SMP support. Signed-off-by: Yehuda Yitschak <yehuday@marvell.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/devicetree/bindings/arm/armada-370-xp-mpic.txt12
1 files changed, 9 insertions, 3 deletions
diff --git a/Documentation/devicetree/bindings/arm/armada-370-xp-mpic.txt b/Documentation/devicetree/bindings/arm/armada-370-xp-mpic.txt
index 70c0dc5f00ed..61df564c0d23 100644
--- a/Documentation/devicetree/bindings/arm/armada-370-xp-mpic.txt
+++ b/Documentation/devicetree/bindings/arm/armada-370-xp-mpic.txt
@@ -6,9 +6,15 @@ Required properties:
- interrupt-controller: Identifies the node as an interrupt controller.
- #interrupt-cells: The number of cells to define the interrupts. Should be 1.
The cell is the IRQ number
+
- reg: Should contain PMIC registers location and length. First pair
for the main interrupt registers, second pair for the per-CPU
- interrupt registers
+ interrupt registers. For this last pair, to be compliant with SMP
+ support, the "virtual" must be use (For the record, these registers
+ automatically map to the interrupt controller registers of the
+ current CPU)
+
+
Example:
@@ -18,6 +24,6 @@ Example:
#address-cells = <1>;
#size-cells = <1>;
interrupt-controller;
- reg = <0xd0020000 0x1000>,
- <0xd0021000 0x1000>;
+ reg = <0xd0020a00 0x1d0>,
+ <0xd0021070 0x58>;
};