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authorMichael Hennerich <michael.hennerich@analog.com>2008-07-14 16:51:57 +0800
committerBryan Wu <cooloney@kernel.org>2008-07-14 16:51:57 +0800
commit68e2fc78e5055740126df8eab0d31005495756c9 (patch)
tree0d43976ff1d3ae8535445f9bcb1687f657f33337 /arch/blackfin/mach-bf561/head.S
parent260d5d3517c67c5b68b4e28c5d3e1e3b73976a90 (diff)
downloadlinux-sh-68e2fc78e5055740126df8eab0d31005495756c9.tar.gz
Blackfin arch: Fix bug - Kernel does not boot if re-program clocks
Don't write conflicting data to EBIU_SDBCTL after the SDRAM is configured. This can cause data corruption, since we might change SDRAM row and column addressing modes. Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
Diffstat (limited to 'arch/blackfin/mach-bf561/head.S')
-rw-r--r--arch/blackfin/mach-bf561/head.S6
1 files changed, 0 insertions, 6 deletions
diff --git a/arch/blackfin/mach-bf561/head.S b/arch/blackfin/mach-bf561/head.S
index 5b8bd40851dd..cf1a2dff01e7 100644
--- a/arch/blackfin/mach-bf561/head.S
+++ b/arch/blackfin/mach-bf561/head.S
@@ -377,12 +377,6 @@ ENTRY(_start_dma_code)
w[p0] = r0.l;
ssync;
- p0.l = LO(EBIU_SDBCTL);
- p0.h = HI(EBIU_SDBCTL); /* SDRAM Memory Bank Control Register */
- r0 = mem_SDBCTL;
- w[p0] = r0.l;
- ssync;
-
P2.H = hi(EBIU_SDGCTL);
P2.L = lo(EBIU_SDGCTL);
R0 = [P2];