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authorGuo Ren <ren_guo@c-sky.com>2018-09-05 14:25:22 +0800
committerGuo Ren <ren_guo@c-sky.com>2018-10-26 00:54:26 +0800
commit735ee005c371b2d8d1dbf0542590d17f1e0a0b2f (patch)
treefb4993c30faf6019610bcd4d51ad1c4a1ab23b6c /arch/csky/abiv1/inc/abi/reg_ops.h
parent991069865796f8ad31ee54aca8a0f1b7a522e94b (diff)
downloadlinux-sh-735ee005c371b2d8d1dbf0542590d17f1e0a0b2f.tar.gz
csky: Misc headers
This patch adds csky registers' definition, bitops, byteorder, asm-offsets codes. Signed-off-by: Guo Ren <ren_guo@c-sky.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/csky/abiv1/inc/abi/reg_ops.h')
-rw-r--r--arch/csky/abiv1/inc/abi/reg_ops.h27
1 files changed, 27 insertions, 0 deletions
diff --git a/arch/csky/abiv1/inc/abi/reg_ops.h b/arch/csky/abiv1/inc/abi/reg_ops.h
new file mode 100644
index 000000000000..a153bd3918f7
--- /dev/null
+++ b/arch/csky/abiv1/inc/abi/reg_ops.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+
+#ifndef __ABI_REG_OPS_H
+#define __ABI_REG_OPS_H
+#include <asm/reg_ops.h>
+
+#define cprcr(reg) \
+({ \
+ unsigned int tmp; \
+ asm volatile("cprcr %0, "reg"\n":"=b"(tmp)); \
+ tmp; \
+})
+
+#define cpwcr(reg, val) \
+({ \
+ asm volatile("cpwcr %0, "reg"\n"::"b"(val)); \
+})
+
+static inline unsigned int mfcr_hint(void)
+{
+ return mfcr("cr30");
+}
+
+static inline unsigned int mfcr_ccr2(void) { return 0; }
+
+#endif /* __ABI_REG_OPS_H */