summaryrefslogtreecommitdiff
path: root/arch
diff options
context:
space:
mode:
authorAlban Bedel <albeu@free.fr>2015-11-17 09:40:07 +0100
committerRalf Baechle <ralf@linux-mips.org>2015-11-20 12:10:09 +0100
commit5011a7e808c9fec643d752c5a495a48f27268a48 (patch)
tree647f26b1da38f51691475358fb0d9a94c583bbd1 /arch
parent95486e4979e56e7da2fbb4fd32eb54d672b1e074 (diff)
downloadlinux-sh-5011a7e808c9fec643d752c5a495a48f27268a48.tar.gz
MIPS: ath79: Fix the DDR control initialization on ar71xx and ar934x
The DDR control initialization needs to know the SoC type, however ath79_detect_sys_type() was called after ath79_ddr_ctrl_init(). Reverse the order to fix the DDR control initialization on ar71xx and ar934x. Signed-off-by: Alban Bedel <albeu@free.fr> Cc: Felix Fietkau <nbd@openwrt.org> Cc: Qais Yousef <qais.yousef@imgtec.com> Cc: Andrew Bresticker <abrestic@chromium.org> CC: stable@vger.kernel.org # v4.2+ Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/11500/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/mips/ath79/setup.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/ath79/setup.c b/arch/mips/ath79/setup.c
index 1ba21204ebe0..9a0013703579 100644
--- a/arch/mips/ath79/setup.c
+++ b/arch/mips/ath79/setup.c
@@ -216,9 +216,9 @@ void __init plat_mem_setup(void)
AR71XX_RESET_SIZE);
ath79_pll_base = ioremap_nocache(AR71XX_PLL_BASE,
AR71XX_PLL_SIZE);
+ ath79_detect_sys_type();
ath79_ddr_ctrl_init();
- ath79_detect_sys_type();
if (mips_machtype != ATH79_MACH_GENERIC_OF)
detect_memory_region(0, ATH79_MEM_SIZE_MIN, ATH79_MEM_SIZE_MAX);