path: root/drivers/pinctrl/intel/pinctrl-sunrisepoint.c
diff options
authorLinus Torvalds <>2020-05-16 13:20:50 -0700
committerLinus Torvalds <>2020-05-16 13:20:50 -0700
commitcf0ca701a01cf631333855831fe48b717ed1f20b (patch)
treedb07a85124eb8d7767733191b989534040af0848 /drivers/pinctrl/intel/pinctrl-sunrisepoint.c
parent18e70f3a7651b420bf5d8ce0a3fd3d1cd9e5b689 (diff)
parentdca4f40742e09ec5d908a7fc2862498e6cf9d911 (diff)
Merge tag 'pinctrl-v5.7-2' of git://
Pull pin control fixes from Linus Walleij: "A bunch of pin control fixes, some a bit overly ripe, sorry about that. We have important systems like Intel laptops and Qualcomm mobile chips covered. - Pad lock register on Intel Sunrisepoint had the wrong offset - Fix pin config setting for the Baytrail GPIO chip - Fix a compilation warning in the Mediatek driver - Fix a function group name in the Actions driver - Fix a behaviour bug in the edge polarity code in the Qualcomm driver - Add a missing spinlock in the Intel Cherryview driver - Add affinity callbacks to the Qualcomm MSMGPIO chip" * tag 'pinctrl-v5.7-2' of git:// pinctrl: qcom: Add affinity callbacks to msmgpio IRQ chip pinctrl: cherryview: Add missing spinlock usage in chv_gpio_irq_handler pinctrl: qcom: fix wrong write in update_dual_edge pinctrl: actions: fix function group name for i2c0_group pinctrl: mediatek: remove shadow variable declaration pinctrl: baytrail: Enable pin configuration setting for GPIO chip pinctrl: sunrisepoint: Fix PAD lock register offset for SPT-H
Diffstat (limited to 'drivers/pinctrl/intel/pinctrl-sunrisepoint.c')
1 files changed, 8 insertions, 7 deletions
diff --git a/drivers/pinctrl/intel/pinctrl-sunrisepoint.c b/drivers/pinctrl/intel/pinctrl-sunrisepoint.c
index 330c8f077b73..4d7a86a5a37b 100644
--- a/drivers/pinctrl/intel/pinctrl-sunrisepoint.c
+++ b/drivers/pinctrl/intel/pinctrl-sunrisepoint.c
@@ -15,17 +15,18 @@
#include "pinctrl-intel.h"
-#define SPT_PAD_OWN 0x020
-#define SPT_PADCFGLOCK 0x0a0
-#define SPT_HOSTSW_OWN 0x0d0
-#define SPT_GPI_IS 0x100
-#define SPT_GPI_IE 0x120
+#define SPT_PAD_OWN 0x020
+#define SPT_H_PADCFGLOCK 0x090
+#define SPT_LP_PADCFGLOCK 0x0a0
+#define SPT_HOSTSW_OWN 0x0d0
+#define SPT_GPI_IS 0x100
+#define SPT_GPI_IE 0x120
#define SPT_COMMUNITY(b, s, e) \
{ \
.barno = (b), \
.padown_offset = SPT_PAD_OWN, \
- .padcfglock_offset = SPT_PADCFGLOCK, \
+ .padcfglock_offset = SPT_LP_PADCFGLOCK, \
.hostown_offset = SPT_HOSTSW_OWN, \
.is_offset = SPT_GPI_IS, \
.ie_offset = SPT_GPI_IE, \
@@ -47,7 +48,7 @@
{ \
.barno = (b), \
.padown_offset = SPT_PAD_OWN, \
- .padcfglock_offset = SPT_PADCFGLOCK, \
+ .padcfglock_offset = SPT_H_PADCFGLOCK, \
.hostown_offset = SPT_HOSTSW_OWN, \
.is_offset = SPT_GPI_IS, \
.ie_offset = SPT_GPI_IE, \