path: root/include
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authorDave Airlie <>2016-04-06 09:48:53 +1000
committerDave Airlie <>2016-04-06 09:48:53 +1000
commit915e846d4b076d1e2da862379c284552fdda0a07 (patch)
tree2314cf2acd494d4124792db36df6ff553c460a72 /include
parent541d8f4d59d79f5d37c8c726f723d42ff307db57 (diff)
parente51f17a049d102a3bc9af3e43f2f45b0538da871 (diff)
Merge tag 'imx-drm-next-2016-04-01' of git:// into drm-fixes
imx-drm: stricter plane parameter checking, dw_hdmi-imx and dmfc fixes - Check whether plane parameters comply with IPU IDMAC limitations and fix planar YUV 4:2:0 U/V offsets and stride - Cleanup encoder in dw_hdmi-imx bind error path and remove a superfluous platform_set_drvdata in dw_hdmi-imx - DMFC setup fixes: lock the ipu_dmfc_init_channel function against concurrent use, rename it to ipu_dmfc_config_wait4eot, and call it after the FIFO size has been determined. * tag 'imx-drm-next-2016-04-01' of git:// drm/imx: Don't set a gamma table size drm/imx: ipuv3-plane: Configure DMFC wait4eot bit after slots are determined gpu: ipu-v3: ipu-dmfc: Rename ipu_dmfc_init_channel to ipu_dmfc_config_wait4eot gpu: ipu-v3: ipu-dmfc: Make function ipu_dmfc_init_channel() return void gpu: ipu-v3: ipu-dmfc: Protect function ipu_dmfc_init_channel() with mutex drm/imx: dw_hdmi: Don't call platform_set_drvdata() drm/imx: dw_hdmi: Call drm_encoder_cleanup() in error path drm/imx: ipuv3-plane: fix planar YUV 4:2:0 support drm/imx: ipuv3-plane: Add more thorough checks for plane parameter limitations gpu: ipu-cpmem: modify ipu_cpmem_set_yuv_planar_full for better control
Diffstat (limited to 'include')
1 files changed, 4 insertions, 3 deletions
diff --git a/include/video/imx-ipu-v3.h b/include/video/imx-ipu-v3.h
index eeba75395f7d..ad66589f2ae6 100644
--- a/include/video/imx-ipu-v3.h
+++ b/include/video/imx-ipu-v3.h
@@ -194,8 +194,9 @@ int ipu_cpmem_set_format_rgb(struct ipuv3_channel *ch,
int ipu_cpmem_set_format_passthrough(struct ipuv3_channel *ch, int width);
void ipu_cpmem_set_yuv_interleaved(struct ipuv3_channel *ch, u32 pixel_format);
void ipu_cpmem_set_yuv_planar_full(struct ipuv3_channel *ch,
- u32 pixel_format, int stride,
- int u_offset, int v_offset);
+ unsigned int uv_stride,
+ unsigned int u_offset,
+ unsigned int v_offset);
void ipu_cpmem_set_yuv_planar(struct ipuv3_channel *ch,
u32 pixel_format, int stride, int height);
int ipu_cpmem_set_fmt(struct ipuv3_channel *ch, u32 drm_fourcc);
@@ -236,7 +237,7 @@ void ipu_dmfc_disable_channel(struct dmfc_channel *dmfc);
int ipu_dmfc_alloc_bandwidth(struct dmfc_channel *dmfc,
unsigned long bandwidth_mbs, int burstsize);
void ipu_dmfc_free_bandwidth(struct dmfc_channel *dmfc);
-int ipu_dmfc_init_channel(struct dmfc_channel *dmfc, int width);
+void ipu_dmfc_config_wait4eot(struct dmfc_channel *dmfc, int width);
struct dmfc_channel *ipu_dmfc_get(struct ipu_soc *ipu, int ipuv3_channel);
void ipu_dmfc_put(struct dmfc_channel *dmfc);