summaryrefslogtreecommitdiff
path: root/arch/arm/boot/dts/bcm-hr2.dtsi
AgeCommit message (Collapse)AuthorLines
2020-05-20ARM: dts: bcm: HR2: Fix PPI interrupt typesHamish Martin-3/+3
These error messages are output when booting on a BCM HR2 system: GIC: PPI11 is secure or misconfigured GIC: PPI13 is secure or misconfigured Per ARM documentation these interrupts are triggered on a rising edge. See ARM Cortex A-9 MPCore Technical Reference Manual, Revision r4p1, Section 3.3.8 Interrupt Configuration Registers. The same issue was resolved for NSP systems in commit 5f1aa51c7a1e ("ARM: dts: NSP: Fix PPI interrupt types"). Fixes: b9099ec754b5 ("ARM: dts: Add Broadcom Hurricane 2 DTS include file") Signed-off-by: Hamish Martin <hamish.martin@alliedtelesis.co.nz> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2019-10-23ARM: dts: bcm: HR2: add label to sp805 watchdogChris Packham-1/+1
This allows boards the option of adding properties or disabling the watchdog entirely. Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2018-09-13ARM: dts: bcm: Fix SPI bus warningsRob Herring-1/+1
dtc has new checks for SPI buses. Fix the warnings in node names. arch/arm/boot/dts/bcm53340-ubnt-unifi-switch8.dtb: Warning (spi_bus_bridge): /axi@18000000/qspi@27200: node name for SPI buses should be 'spi' arch/arm/boot/dts/bcm958525er.dtb: Warning (spi_bus_bridge): /axi/qspi@27200: node name for SPI buses should be 'spi' arch/arm/boot/dts/bcm958525xmc.dtb: Warning (spi_bus_bridge): /axi/qspi@27200: node name for SPI buses should be 'spi' arch/arm/boot/dts/bcm958622hr.dtb: Warning (spi_bus_bridge): /axi/qspi@27200: node name for SPI buses should be 'spi' arch/arm/boot/dts/bcm958625hr.dtb: Warning (spi_bus_bridge): /axi/qspi@27200: node name for SPI buses should be 'spi' arch/arm/boot/dts/bcm988312hr.dtb: Warning (spi_bus_bridge): /axi/qspi@27200: node name for SPI buses should be 'spi' Cc: Ray Jui <rjui@broadcom.com> Cc: Scott Branden <sbranden@broadcom.com> Cc: Jon Mason <jonmason@broadcom.com> Cc: bcm-kernel-feedback-list@broadcom.com Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2018-06-18ARM: dts: HR2: Fix interrupt types for i2c and PCIeFlorian Fainelli-12/+12
The i2c and PCIe controllers had an incorrect type which should have been set to IRQ_TYPE_LEVEL_HIGH, fix that. Fixes: b9099ec754b5 ("ARM: dts: Add Broadcom Hurricane 2 DTS include file") Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2017-10-12ARM: dts: Add Broadcom Hurricane 2 DTS include fileFlorian Fainelli-0/+368
Describe the Broadcom Hurricane 2 SoC comprised of a Cortex-A9 CPU complex along with standard iProc peripherals: * timers * SPI controller * NAND controller * a single AMAC (Ethernet MAC controller) * dual PCIe controllers The design is largely similar to existing iProc-based SoCs such as Northstar Plus. Acked-by: Jon Mason <jon.mason@broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>