path: root/arch/csky/abiv2/cacheflush.c
AgeCommit message (Collapse)AuthorLines
2020-02-21csky: Add flush_icache_mm to defer flush icache allGuo Ren-0/+55
Some CPUs don't support instruction to maintain the whole smp cores' icache. Using icache.all + IPI casue a lot on performace and using defer mechanism could reduce the number of calling icache _flush_all functions. Signed-off-by: Guo Ren <>
2020-02-21csky: Enable defer flush_dcache_page for abiv2 cpus (807/810/860)Guo Ren-6/+8
Instead of flushing cache per update_mmu_cache() called, we use flush_dcache_page to reduce the frequency of flashing the cache. As abiv2 cpus are all PIPT for icache & dcache, we needn't handle dcache aliasing problem. But their icache can't snoop dcache, so we still need sync_icache_dcache in update_mmu_cache(). Signed-off-by: Guo Ren <>
2020-02-21csky: Remove unnecessary flush_icache_* implementationGuo Ren-23/+0
The abiv2 CPUs are all PIPT cache, so there is no need to implement flush_icache_page function. The function flush_icache_user_range hasn't been used, so just remove it. The function flush_cache_range is not necessary for PIPT cache when tlb mapping changed. Signed-off-by: Guo Ren <>
2019-04-22csky: Fixup wrong update_mmu_cache implementationGuo Ren-11/+2
In our stress test, we found some crash problem caused by: if (!(vma->vm_flags & VM_EXEC)) return; in update_mmu_cache(). Seems current update_mmu_cache implementation is wrong and we retread to the conservative implementation. Also the usage of kmap_atomic in update_mmu_cache is risky, page-virtual may be scheduled out and changed, so we must use preempt_disable & pagefault_disable which is called by kmap_atomic(). Signed-off-by: Guo Ren <> Cc: Arnd Bergmann <>
2018-10-25csky: Cache and TLB routinesGuo Ren-0/+60
This patch adds cache and tlb sync codes for abiv1 & abiv2. Signed-off-by: Guo Ren <> Reviewed-by: Arnd Bergmann <>