path: root/arch/csky/abiv2/inc/abi/cacheflush.h
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2020-02-21csky: Add flush_icache_mm to defer flush icache allGuo Ren-3/+11
Some CPUs don't support instruction to maintain the whole smp cores' icache. Using icache.all + IPI casue a lot on performace and using defer mechanism could reduce the number of calling icache _flush_all functions. Signed-off-by: Guo Ren <>
2020-02-21csky: Optimize abiv2 copy_to_user_page with VM_EXECGuo Ren-1/+3
Only when vma is for VM_EXEC, we need sync dcache & icache. eg: - gdb ptrace modify user space instruction code area. Add VM_EXEC condition to reduce unnecessary cache flush. The abiv1 cpus' cache are all VIPT, so we still need to deal with dcache aliasing problem. But there is optimized way to use cache color, just like what's done in arch/csky/abiv1/inc/abi/page.h. Signed-off-by: Guo Ren <>
2020-02-21csky: Enable defer flush_dcache_page for abiv2 cpus (807/810/860)Guo Ren-2/+10
Instead of flushing cache per update_mmu_cache() called, we use flush_dcache_page to reduce the frequency of flashing the cache. As abiv2 cpus are all PIPT for icache & dcache, we needn't handle dcache aliasing problem. But their icache can't snoop dcache, so we still need sync_icache_dcache in update_mmu_cache(). Signed-off-by: Guo Ren <>
2020-02-21csky: Remove unnecessary flush_icache_* implementationGuo Ren-11/+2
The abiv2 CPUs are all PIPT cache, so there is no need to implement flush_icache_page function. The function flush_icache_user_range hasn't been used, so just remove it. The function flush_cache_range is not necessary for PIPT cache when tlb mapping changed. Signed-off-by: Guo Ren <>
2018-10-25csky: Cache and TLB routinesGuo Ren-0/+46
This patch adds cache and tlb sync codes for abiv1 & abiv2. Signed-off-by: Guo Ren <> Reviewed-by: Arnd Bergmann <>