path: root/arch/riscv/kernel/sys_riscv.c
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2020-06-18RISC-V: Don't allow write+exec only page mapping request in mmapYash Shah-0/+6
As per the table 4.4 of version "20190608-Priv-MSU-Ratified" of the RISC-V instruction set manual[0], the PTE permission bit combination of "write+exec only" is reserved for future use. Hence, don't allow such mapping request in mmap call. An issue is been reported by David Abdurachmanov, that while running stress-ng with "sysbadaddr" argument, RCU stalls are observed on RISC-V specific kernel. This issue arises when the stress-sysbadaddr request for pages with "write+exec only" permission bits and then passes the address obtain from this mmap call to various system call. For the riscv kernel, the mmap call should fail for this particular combination of permission bits since it's not valid. [0]: Signed-off-by: Yash Shah <> Reported-by: David Abdurachmanov <> [Palmer: Refer to the latest ISA specification at the only link I could find, and update the terminology.] Signed-off-by: Palmer Dabbelt <>
2019-06-05treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286Thomas Gleixner-9/+1
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation version 2 this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 97 file(s). Signed-off-by: Thomas Gleixner <> Reviewed-by: Allison Randal <> Reviewed-by: Alexios Zavras <> Cc: Link: Signed-off-by: Greg Kroah-Hartman <>
2018-08-28RISC-V: Use a less ugly workaround for unused variable warningsPalmer Dabbelt-14/+1
Thanks to Christoph Hellwig for pointing out a cleaner way to do this, as my approach was quite ugly. CC: Christoph Hellwig <> Signed-off-by: Palmer Dabbelt <>
2018-08-20RISC-V: Define sys_riscv_flush_icache when SMP=nPalmer Dabbelt-2/+10
This would be necessary to make non-SMP builds work, but there is another error in the implementation of our syscall linkage that actually just causes sys_riscv_flush_icache to never build. I've build tested this on allnoconfig and allnoconfig+SMP=y, as well as defconfig like normal. CC: Christoph Hellwig <> CC: Guenter Roeck <> In-Reply-To: <> In-Reply-To: <> Signed-off-by: Palmer Dabbelt <>
2018-04-02mm: add ksys_mmap_pgoff() helper; remove in-kernel calls to sys_mmap_pgoff()Dominik Brodowski-2/+2
Using this helper allows us to avoid the in-kernel calls to the sys_mmap_pgoff() syscall. The ksys_ prefix denotes that this function is meant as a drop-in replacement for the syscall. In particular, it uses the same calling convention as sys_mmap_pgoff(). This patch is part of a series which removes in-kernel calls to syscalls. On this basis, the syscall entry path can be streamlined. For details, see Cc: Andrew Morton <> Cc: Signed-off-by: Dominik Brodowski <>
2017-12-11RISC-V: Logical vs Bitwise typoDan Carpenter-1/+1
In the current code, there is a ! logical NOT where a bitwise ~ NOT was intended. It means that we never return -EINVAL. Signed-off-by: Dan Carpenter <> Signed-off-by: Palmer Dabbelt <>
2017-11-30RISC-V: Clean up an unused includePalmer Dabbelt-1/+0
We used to have some cmpxchg syscalls. They're no longer there, so we no longer need the include. CC: Christoph Hellwig <> Signed-off-by: Palmer Dabbelt <>
2017-11-30RISC-V: Allow userspace to flush the instruction cacheAndrew Waterman-0/+32
Despite RISC-V having a direct 'fence.i' instruction available to userspace (which we can't trap!), that's not actually viable when running on Linux because the kernel might schedule a process on another hart. There is no way for userspace to handle this without invoking the kernel (as it doesn't know the thread->hart mappings), so we've defined a RISC-V specific system call to flush the instruction cache. This patch adds both a system call and a VDSO entry. If possible, we'd like to avoid having the system call be considered part of the user-facing ABI and instead restrict that to the VDSO entry -- both just in general to avoid having additional user-visible ABI to maintain, and because we'd prefer that users just call the VDSO entry because there might be a better way to do this in the future (ie, one that doesn't require entering the kernel). Signed-off-by: Andrew Waterman <> Signed-off-by: Palmer Dabbelt <>
2017-09-26RISC-V: User-facing APIPalmer Dabbelt-0/+49
This patch contains code that is in some way visible to the user: including via system calls, the VDSO, module loading and signal handling. It also contains some generic code that is ABI visible. Signed-off-by: Palmer Dabbelt <>