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2016-04-28sh: do not perform IPI-based cache flush except on boards that need itRich Felker-0/+3
Signed-off-by: Rich Felker <>
2016-04-28sh: add SMP support for J2Rich Felker-0/+144
Signed-off-by: Rich Felker <>
2016-04-28sh: SMP support for SH2 entry.SRich Felker-0/+50
The SH2 version of entry.S uses global variables, which need to be cpu-local in order to work with SMP. For ease of access from asm, simply use arrays indexed by cpu number, and require the availability of an address (mmio register or properly setup per-cpu memory) from which the current cpu's index can be read. Signed-off-by: Rich Felker <>
2016-04-28sh: add working futex atomic ops on userspace addresses for smpRich Felker-124/+134
The version of futex.h in asm-generic should really be adapted to do the same thing so that this hideous code does not have to be duplicated per-arch. Signed-off-by: Rich Felker <>
2016-04-28sh: add J2 atomics using the cas.l instructionRich Felker-210/+469
Signed-off-by: Rich Felker <>
2016-04-28sh: add device tree source for J2 FPGA on Mimas v2 boardj2-stableRich Felker-0/+98
Signed-off-by: Rich Felker <>
2016-04-28sh: add defconfig for J-Core J2Rich Felker-0/+38
This defconfig is intended not to be specific to a particular board; it enables drivers for all currently-supported hardware, and should be updated to include additional drivers as they are added. Signed-off-by: Rich Felker <>
2016-04-28sh: add AT_HWCAP flag for J-Core cas.l instructionRich Felker-0/+3
Signed-off-by: Rich Felker <>
2016-04-28sh: add support for J-Core J2 processorRich Felker-4/+131
Signed-off-by: Rich Felker <>
2016-04-28sh: fix futex/robust_list on nommu modelsRich Felker-0/+1
The futex cmpxchg runtime testing in kernel/futex.c depends on accesses to address 0 producing EFAULT, which obviously does not work on nommu. Since SH always has cmpxchg, disable the broken runtime detection. At some point this should be fixed at the kernel/futex.c level. UP machines can always provide a working cmpxchg with interrupt masking, and SMP cannot function without a working cmpxchg anyway. Signed-off-by: Rich Felker <>
2016-04-28sh: disable aliased page logic on NOMMU modelsRich Felker-0/+8
SH3/4 (with MMU) have a virtually indexed cache, requiring explicit work to avoid consistency problems arising from having the same physical address range cached in multiple cache lines. This is unneeded for the NOMMU case, and some of the resulting code paths (kmap_coherent) don't work. SH2 only avoided this problem by having a 4-way associative cache with way size equal to the page size (4k), yielding no cache index bits outside of the page offset and thus no aliases. Signed-off-by: Rich Felker <>
2016-04-28sh: make sigcontext definition consistent across fpu/nofpu modelsRich Felker-3/+0
Up until now, the SH version of the sigcontext structure, and thus mcontext_t/ucontext_t, varied depending on the cpu model the kernel was built to run on. SH-4 (including SH-4A) and SH-2A used the form with space for FPU registers, and everything else used a form that omitted them. From a userspace perspective, however, the structure layout must be fixed for a given ABI. Traditionally glibc and uClibc used the form with space for FPU registers only when __SH4__ (which implies FPU; __SH4_NOFPU__ is the predefined macro for SH-4 but with no-FPU ABI) was defined. As a result: - SH-4 no-FPU programs never matched kernel sigcontext. - SH-3 programs did not match kernel sigcontext if run on SH-4, despite an apparent intent that they be compatible. - SH-2 and SH-2A programs (using uClibc) did not match kernel sigcontext if run on SH-2A. The mismatch might seem inconsequential because it occurs at the end of the sigcontext structure, but sigcontext is embedded as uc_mcontext in ucontext_t, where it is followed by uc_sigmask, an important member for signal handlers to have access to. In particular, access to uc_sigmask is necessary for a correct implementation of thread cancellation. It would be possible to retain support for both sigcontext ABIs via a personality mechanism, but since many configurations were already broken and nobody noticed, and since there are very few if any users of legacy no-FPU models anymore, I have opted to just remove the variation and always include space for the FPU registers in sigcontext. This was proposed and discussed on a thread "SH sigcontext ABI is broken" cross-posted to linux-sh, libc-alpha, and musl libc lists in June 2015, and no objections were raised. Signed-off-by: Rich Felker <>
2016-04-28sh: add support for linking a builtin device tree blob in the kernelRich Felker-3/+41
Signed-off-by: Rich Felker <>
2016-04-28sh: cmpxchg: fix a bit shift bug in big_endian osPan Xinhui-1/+1
Correct bitoff in big endian OS. Current code works correctly for 1 byte but not for 2 bytes. Fixes: 3226aad81aa6 ("sh: support 1 and 2 byte xchg") Signed-off-by: Pan Xinhui <> Acked-by: Michael S. Tsirkin <> Signed-off-by: Rich Felker <>
2016-04-23Merge branch 'x86-urgent-for-linus' of ↵Linus Torvalds-0/+13
git:// Pull x86 fixes from Ingo Molnar: "Misc fixes: two EDAC driver fixes, a Xen crash fix, a HyperV log spam fix and a documentation fix" * 'x86-urgent-for-linus' of git:// x86 EDAC, sb_edac.c: Take account of channel hashing when needed x86 EDAC, sb_edac.c: Repair damage introduced when "fixing" channel address x86/mm/xen: Suppress hugetlbfs in PV guests x86/doc: Correct limits in Documentation/x86/x86_64/mm.txt x86/hyperv: Avoid reporting bogus NMI status for Gen2 instances
2016-04-22Merge tag 'arm64-fixes' of ↵Linus Torvalds-6/+18
git:// Pull arm64 fixes from Catalin Marinas: - Cache invalidation fix for early CPU boot status update (incorrect cacheline) - of_put_node() missing in the spin_table code - EL1/El2 early init inconsistency when Virtualisation Host Extensions are present - RCU warning fix in the arm_pmu.c driver * tag 'arm64-fixes' of git:// arm64: Fix EL1/EL2 early init inconsistencies with VHE drivers/perf: arm-pmu: fix RCU usage on pmu resume from low-power arm64: spin-table: add missing of_node_put() arm64: fix invalidation of wrong __early_cpu_boot_status cacheline
2016-04-22Merge tag 'powerpc-4.6-3' of ↵Linus Torvalds-11/+16
git:// Pull powerpc fixes from Michael Ellerman: "Three powerpc cpu feature fixes from Anton Blanchard: - scan_features() updated incorrect bits for REAL_LE - update cpu_user_features2 in scan_features() - update TM user feature bits in scan_features()" * tag 'powerpc-4.6-3' of git:// powerpc: Update TM user feature bits in scan_features() powerpc: Update cpu_user_features2 in scan_features() powerpc: scan_features() updates incorrect bits for REAL_LE
2016-04-22x86/mm/xen: Suppress hugetlbfs in PV guestsJan Beulich-0/+1
Huge pages are not normally available to PV guests. Not suppressing hugetlbfs use results in an endless loop of page faults when user mode code tries to access a hugetlbfs mapped area (since the hypervisor denies such PTEs to be created, but error indications can't be propagated out of xen_set_pte_at(), just like for various of its siblings), and - once killed in an oops like this: kernel BUG at .../fs/hugetlbfs/inode.c:428! invalid opcode: 0000 [#1] SMP ... RIP: e030:[<ffffffff811c333b>] [<ffffffff811c333b>] remove_inode_hugepages+0x25b/0x320 ... Call Trace: [<ffffffff811c3415>] hugetlbfs_evict_inode+0x15/0x40 [<ffffffff81167b3d>] evict+0xbd/0x1b0 [<ffffffff8116514a>] __dentry_kill+0x19a/0x1f0 [<ffffffff81165b0e>] dput+0x1fe/0x220 [<ffffffff81150535>] __fput+0x155/0x200 [<ffffffff81079fc0>] task_work_run+0x60/0xa0 [<ffffffff81063510>] do_exit+0x160/0x400 [<ffffffff810637eb>] do_group_exit+0x3b/0xa0 [<ffffffff8106e8bd>] get_signal+0x1ed/0x470 [<ffffffff8100f854>] do_signal+0x14/0x110 [<ffffffff810030e9>] prepare_exit_to_usermode+0xe9/0xf0 [<ffffffff814178a5>] retint_user+0x8/0x13 This is CVE-2016-3961 / XSA-174. Reported-by: Vitaly Kuznetsov <> Signed-off-by: Jan Beulich <> Cc: Andrew Morton <> Cc: Andy Lutomirski <> Cc: Boris Ostrovsky <> Cc: Borislav Petkov <> Cc: Brian Gerst <> Cc: David Vrabel <> Cc: Denys Vlasenko <> Cc: H. Peter Anvin <> Cc: Juergen Gross <> Cc: Linus Torvalds <> Cc: Luis R. Rodriguez <> Cc: Peter Zijlstra <> Cc: Thomas Gleixner <> Cc: Toshi Kani <> Cc: Cc: xen-devel <> Link: Signed-off-by: Ingo Molnar <>
2016-04-21arm64: Fix EL1/EL2 early init inconsistencies with VHEDave Martin-0/+10
When using the Virtualisation Host Extensions, EL1 is not used in the host and requires no separate configuration. In addition, with VHE enabled, non-hyp-specific EL2 configuration that does not need to be done early will be done anyway in __cpu_setup via the _EL1 system register aliases. In particular, the layout and definition of CPTR_EL2 are changed by enabling VHE so that they resemble CPACR_EL1, so existing code to initialise CPTR_EL2 becomes architecturally wrong in this case. This patch simply skips the affected initialisation code in the non-VHE case. Signed-off-by: Dave Martin <> Reviewed-by: Marc Zyngier <> Signed-off-by: Catalin Marinas <>
2016-04-21Merge branch 'fixes' of git:// Torvalds-3/+4
Pull ARM fixes from Russell King: "Three further fixes for ARM. Alexandre Courbot was having problems with DMA allocations with the GFP flags affecting where the tracking data was being allocated from. Vladimir Murzin noticed that the CPU feature code was not entirely correct, which can cause some features to be misreported" * 'fixes' of git:// ARM: 8564/1: fix cpu feature extracting helper ARM: 8563/1: fix demoting HWCAP_SWP ARM: 8551/2: DMA: Fix kzalloc flags in __dma_alloc
2016-04-20Merge branch 'linus' of ↵Linus Torvalds-2/+2
git:// Pull crypto fixes from Herbert Xu: "This fixes the following issues: - Incorrect output buffer size calculation in rsa-pkcs1pad - Uninitialised padding bytes on exported state in ccp driver - Potentially freed pointer used on completion callback in sha1-mb" * 'linus' of git:// crypto: ccp - Prevent information leakage on export crypto: sha1-mb - use corrcet pointer while completing jobs crypto: rsa-pkcs1pad - fix dst len
2016-04-20arm64: spin-table: add missing of_node_put()Masahiro Yamada-5/+6
Since of_get_cpu_node() increments refcount, the node should be put. Signed-off-by: Masahiro Yamada <> Acked-by: Will Deacon <> Signed-off-by: Catalin Marinas <>
2016-04-19ARM: 8564/1: fix cpu feature extracting helperVladimir Murzin-1/+1
Commit b8c9592 "ARM: 8318/1: treat CPU feature register fields as signed quantities" introduced helper to extract signed quantities of 4-bit blocks. However, with a current code feature with value 0b1000 isn't rejected as negative. So fix the "if" condition. Reported-by: Jonathan Brawn <> Signed-off-by: Vladimir Murzin <> Acked-by: Ard Biesheuvel <> Signed-off-by: Russell King <>
2016-04-19ARM: 8563/1: fix demoting HWCAP_SWPVladimir Murzin-1/+1
Commit b8c9592 "ARM: 8318/1: treat CPU feature register fields as signed quantities" accidentally altered cpuid register used to demote HWCAP_SWP. ARM ARM says that SyncPrim_instrs bits in ID_ISAR3 should be used with SynchPrim_instrs_frac from ID_ISAR4. So, follow this rule. Signed-off-by: Vladimir Murzin <> Acked-by: Ard Biesheuvel <> Signed-off-by: Russell King <>
2016-04-18Merge branch 'for-linus' of ↵Linus Torvalds-1/+8
git:// Pull s390 fixes from Martin Schwidefsky: "A couple of bug fixes" * 'for-linus' of git:// s390: add CPU_BIG_ENDIAN config option s390/spinlock: avoid yield to non existent cpu s390/dcssblk: fix possible deadlock in remove vs. per-device attributes s390/seccomp: include generic seccomp header file s390/pci: add extra padding to function measurement block s390/scm_blk: fix deadlock for requests != REQ_TYPE_FS
2016-04-18arm64: fix invalidation of wrong __early_cpu_boot_status cachelineArd Biesheuvel-1/+2
In head.S, the str_l macro, which takes a source register, a symbol name and a temp register, is used to store a status value to the variable __early_cpu_boot_status. Subsequently, the value of the temp register is reused to invalidate any cachelines covering this variable. However, since str_l resolves to adrp \tmp, \sym str \src, [\tmp, :lo12:\sym] the temp register never actually holds the address of the variable but only of the 4 KB window that covers it, and reusing it leads to the wrong cacheline being invalidated. So instead, take the address explicitly before doing the store, and reuse that value to perform the cache invalidation. Fixes: bb9052744f4b ("arm64: Handle early CPU boot failures") Signed-off-by: Ard Biesheuvel <> Acked-by: Mark Rutland <> Acked-by: Suzuki K Poulose <> Signed-off-by: Catalin Marinas <>
2016-04-18powerpc: Update TM user feature bits in scan_features()Anton Blanchard-4/+5
We need to update the user TM feature bits (PPC_FEATURE2_HTM and PPC_FEATURE2_HTM) to mirror what we do with the kernel TM feature bit. At the moment, if firmware reports TM is not available we turn off the kernel TM feature bit but leave the userspace ones on. Userspace thinks it can execute TM instructions and it dies trying. This (together with a QEMU patch) fixes PR KVM, which doesn't currently support TM. Signed-off-by: Anton Blanchard <> Cc: Signed-off-by: Michael Ellerman <>
2016-04-18powerpc: Update cpu_user_features2 in scan_features()Anton Blanchard-8/+11
scan_features() updates cpu_user_features but not cpu_user_features2. Amongst other things, cpu_user_features2 contains the user TM feature bits which we must keep in sync with the kernel TM feature bit. Signed-off-by: Anton Blanchard <> Cc: Signed-off-by: Michael Ellerman <>
2016-04-18powerpc: scan_features() updates incorrect bits for REAL_LEAnton Blanchard-1/+2
The REAL_LE feature entry in the ibm_pa_feature struct is missing an MMU feature value, meaning all the remaining elements initialise the wrong values. This means instead of checking for byte 5, bit 0, we check for byte 0, bit 0, and then we incorrectly set the CPU feature bit as well as MMU feature bit 1 and CPU user feature bits 0 and 2 (5). Checking byte 0 bit 0 (IBM numbering), means we're looking at the "Memory Management Unit (MMU)" feature - ie. does the CPU have an MMU. In practice that bit is set on all platforms which have the property. This means we set CPU_FTR_REAL_LE always. In practice that seems not to matter because all the modern cpus which have this property also implement REAL_LE, and we've never needed to disable it. We're also incorrectly setting MMU feature bit 1, which is: #define MMU_FTR_TYPE_8xx 0x00000002 Luckily the only place that looks for MMU_FTR_TYPE_8xx is in Book3E code, which can't run on the same cpus as scan_features(). So this also doesn't matter in practice. Finally in the CPU user feature mask, we're setting bits 0 and 2. Bit 2 is not currently used, and bit 0 is: #define PPC_FEATURE_PPC_LE 0x00000001 Which says the CPU supports the old style "PPC Little Endian" mode. Again this should be harmless in practice as no 64-bit CPUs implement that mode. Fix the code by adding the missing initialisation of the MMU feature. Also add a comment marking CPU user feature bit 2 (0x4) as reserved. It would be unsafe to start using it as old kernels incorrectly set it. Fixes: 44ae3ab3358e ("powerpc: Free up some CPU feature bits by moving out MMU-related features") Signed-off-by: Anton Blanchard <> Cc: [mpe: Flesh out changelog, add comment reserving 0x4] Signed-off-by: Michael Ellerman <>
2016-04-16x86/hyperv: Avoid reporting bogus NMI status for Gen2 instancesVitaly Kuznetsov-0/+12
Generation2 instances don't support reporting the NMI status on port 0x61, read from there returns 'ff' and we end up reporting nonsensical PCI error (as there is no PCI bus in these instances) on all NMIs: NMI: PCI system error (SERR) for reason ff on CPU 0. Dazed and confused, but trying to continue Fix the issue by overriding x86_platform.get_nmi_reason. Use 'booted on EFI' flag to detect Gen2 instances. Signed-off-by: Vitaly Kuznetsov <> Cc: Alexander Shishkin <> Cc: Arnaldo Carvalho de Melo <> Cc: Cathy Avery <> Cc: Haiyang Zhang <> Cc: Jiri Olsa <> Cc: K. Y. Srinivasan <> Cc: Linus Torvalds <> Cc: Peter Zijlstra <> Cc: Thomas Gleixner <> Cc: Link: Signed-off-by: Ingo Molnar <>
2016-04-15Merge branch 'parisc-4.6-4' of ↵Linus Torvalds-168/+114
git:// Pull parisc ftrace fixes from Helge Deller: "This is (most likely) the last pull request for v4.6 for the parisc architecture. It fixes the FTRACE feature for parisc, which is horribly broken since quite some time and doesn't even compile. This patch just fixes the bare minimum (it actually removes more lines than it adds), so that the function tracer works again on 32- and 64bit kernels. I've queued up additional patches on top of this patch which e.g. add the syscall tracer, but those have to wait for the merge window for v4.7." * 'parisc-4.6-4' of git:// parisc: Fix ftrace function tracer
2016-04-15s390: add CPU_BIG_ENDIAN config optionHeiko Carstens-0/+3
Make sure that s390 appears to be a big endian machine by defining this config option. Without this s390 appears to be little endian as seen by e.g. the recordmount script: "perl ./scripts/ "s390" "little" "64"" This has no practical impact within the script since the endian variable is only evaluated for mips. However there are already a couple of common code places which evaluate this config option. None of them is relevant for s390 currently though. To avoid any issues in the future (and fix the recordmcount oddity) add the new config option. Signed-off-by: Heiko Carstens <> Signed-off-by: Martin Schwidefsky <>
2016-04-15s390/spinlock: avoid yield to non existent cpuHeiko Carstens-0/+1
arch_spin_lock_wait_flags() checks if a spinlock is not held before trying a compare and swap instruction. If the lock is unlocked it tries the compare and swap instruction, however if a different cpu grabbed the lock in the meantime the instruction will fail as expected. Subsequently the arch_spin_lock_wait_flags() incorrectly tries to figure out if the cpu that holds the lock is running. However it is using the wrong cpu number for this (-1) and then will also yield the current cpu to the wrong cpu. Fix this by adding a missing continue statement. Fixes: 470ada6b1a1d ("s390/spinlock: refactor arch_spin_lock_wait[_flags]") Signed-off-by: Heiko Carstens <> Acked-by: Martin Schwidefsky <>
2016-04-15crypto: sha1-mb - use corrcet pointer while completing jobsXiaodong Liu-2/+2
In sha_complete_job, incorrect mcryptd_hash_request_ctx pointer is used when check and complete other jobs. If the memory of first completed req is freed, while still completing other jobs in the func, kernel will crash since NULL pointer is assigned to RIP. Cc: <> Signed-off-by: Xiaodong Liu <> Acked-by: Tim Chen <> Signed-off-by: Herbert Xu <>
2016-04-15ARM: 8551/2: DMA: Fix kzalloc flags in __dma_allocAlexandre Courbot-1/+2
Commit 19e6e5e5392b ("ARM: 8547/1: dma-mapping: store buffer information") allocates a structure meant for internal buffer management with the GFP flags of the buffer itself. This can trigger the following safeguard in the slab/slub allocator: if (unlikely(flags & GFP_SLAB_BUG_MASK)) { pr_emerg("gfp: %un", flags & GFP_SLAB_BUG_MASK); BUG(); } Fix this by filtering the flags that make the slab allocator unhappy. Signed-off-by: Alexandre Courbot <> Acked-by: Rabin Vincent <> Signed-off-by: Russell King <>
2016-04-14Merge branch 'x86-urgent-for-linus' of ↵Linus Torvalds-3/+51
git:// Pull x86 fixes from Ingo Molnar: "Misc fixes: a binutils fix, an lguest fix, an mcelog fix and a missing documentation fix" * 'x86-urgent-for-linus' of git:// x86/mce: Avoid using object after free in genpool lguest, x86/entry/32: Fix handling of guest syscalls using interrupt gates x86/build: Build compressed x86 kernels as PIE x86/mm/pkeys: Add missing Documentation
2016-04-14Revert "x86: remove the kernel code/data/bss resources from /proc/iomem"Linus Torvalds-0/+37
This reverts commit c4004b02f8e5b9ce357a0bb1641756cc86962664. Sadly, my hope that nobody would actually use the special kernel entries in /proc/iomem were dashed by kexec. Which reads /proc/iomem explicitly to find the kernel base address. Nasty. Anyway, that means we can't do the sane and simple thing and just remove the entries, and we'll instead have to mask them out based on permissions. Reported-by: Zhengyu Zhang <> Reported-by: Dave Young <> Reported-by: Freeman Zhang <> Reported-by: Emrah Demir <> Reported-by: Baoquan He <> Signed-off-by: Linus Torvalds <>
2016-04-14parisc: Fix ftrace function tracerHelge Deller-168/+114
Fix the FTRACE function tracer for 32- and 64-bit kernel. The former code was horribly broken. Reimplement most coding in assembly and utilize optimizations, e.g. put mcount() and ftrace_stub() into one L1 cacheline. Signed-off-by: Helge Deller <>
2016-04-13Merge tag 'sh-fixes-4.6-rc1' of git:// Torvalds-10/+3
Pull arch/sh fixes from Rich Felker: "Fixes for two arch/sh build regressions that appeared in 4.6-rc1, one introduced by me, and one caused by changes elsewhere" * tag 'sh-fixes-4.6-rc1' of git:// sh: fix function signature of cpu_coregroup_mask to match pointer type sh: fix smp-shx3 build regression from removal of arch localtimer
2016-04-13Merge branch 'for-linus' of ↵Linus Torvalds-7/+1
git:// Pull m68knommu/coldfire fix from Greg Ungerer: "Only a single change that removes a local arch specific gpio bus sysfs device that now clashes with the generic gpio bus sysfs device interface" * 'for-linus' of git:// m68k/gpio: remove arch specific sysfs bus device
2016-04-13Merge tag 'armsoc-fixes' of ↵Linus Torvalds-52/+80
git:// Pull ARM SoC fixes from Olof Johansson: "A batch of fixes for -rc4, for various platforms. Nothing really substantial and worth pointing out in particular; small fixes for various bugs, see shortlog for details" * tag 'armsoc-fixes' of git:// ARM: sa1100: remove references to the defunct bus: uniphier-system-bus: fix condition of overlap check ARM: uniphier: drop weird sizeof() ARM: dts: am335x-baltos-ir5221: fix cpsw_emac0 link type ARM: OMAP: Correct interrupt type for ARM TWD ARM: DRA722: Add ID detect for Silicon Rev 2.0 ARM: dts: am43xx: fix edma memcpy channel allocation ARM: dts: AM43x-epos: Fix clk parent for synctimer ARM: OMAP2: Fix up interconnect barrier initialization for DRA7 documentation: Fix pinctrl documentation for Meson8 / Meson8b ARM: dts: amlogic: Split pinctrl device for Meson8 / Meson8b ARM: mvebu: Correct unit address for linksys bus: mvebu-mbus: use %pa to print phys_addr_t arm64: dts: vulcan: Update PCI ranges ARM: u8500_defconfig: turn on the Synaptics RMI4 driver ARM: pxa: fix the number of DMA requestor lines ARM: OMAP2+: hwmod: Fix updating of sysconfig register ARM: OMAP2+: Use srst_udelay for USB on dm814x
2016-04-13Merge tag 'for-linus' of git:// Torvalds-25/+64
Pull KVM fixes from Radim Krčmář: "ARM fixes: - Wrong indentation in the PMU code from the merge window - A long-time bug occuring with running ntpd on the host, candidate for stable - Properly handle (and warn about) the unsupported configuration of running on systems with less than 40 bits of PA space - More fixes to the PM and hotplug notifier stuff from the merge window x86: - leak of guest xcr0 (typically shows up as SIGILL) - new maintainer (who is sending the pull request too) - fix for merge window regression - fix for guest CPUID" Paolo Bonzini points out: "For the record, this tag is signed by me because I prepared the pull request. Further pull requests for 4.6 will be signed and sent out by Radim directly" * tag 'for-linus' of git:// KVM: x86: mask CPUID(0xD,0x1).EAX against host value kvm: x86: do not leak guest xcr0 into host interrupt handlers KVM: MMU: fix permission_fault() KVM: new maintainer on the block arm64: KVM: unregister notifiers in hyp mode teardown path arm64: KVM: Warn when PARange is less than 40 bits KVM: arm/arm64: Handle forward time correction gracefully arm64: KVM: Add braces to multi-line if statement in virtual PMU code
2016-04-13x86/mce: Avoid using object after free in genpoolTony Luck-2/+2
When we loop over all queued machine check error records to pass them to the registered notifiers we use llist_for_each_entry(). But the loop calls gen_pool_free() for the entry in the body of the loop - and then the iterator looks at node->next after the free. Use llist_for_each_entry_safe() instead. Signed-off-by: Tony Luck <> Signed-off-by: Borislav Petkov <> Cc: <> Cc: Gong Chen <> Cc: Linus Torvalds <> Cc: Peter Zijlstra <> Cc: Thomas Gleixner <> Cc: linux-edac <> Link: Link: Signed-off-by: Ingo Molnar <>
2016-04-12Merge tag 'mvebu-fixes-4.6-1' of git:// into fixesOlof Johansson-1/+1
mvebu fixes for 4.6 (part 1) - fix USB adress register for Linksys Armada 388 based boards - fix build warning in mvebu-mbus * tag 'mvebu-fixes-4.6-1' of git:// ARM: mvebu: Correct unit address for linksys bus: mvebu-mbus: use %pa to print phys_addr_t Signed-off-by: Olof Johansson <>
2016-04-12ARM: sa1100: remove references to the defunct handhelds.orgLinus Walleij-8/+2
The website has been down for a long time and is likely never coming back online. Signed-off-by: Linus Walleij <> Signed-off-by: Olof Johansson <>
2016-04-12Merge tag 'pxa-fixes-v4.6' of into fixesOlof Johansson-0/+1
ARM: pxa: fixes for v4.6 There is only a single fix for dma requestor lines initial setup, triggered by dmaengine previous fix. * tag 'pxa-fixes-v4.6' of ARM: pxa: fix the number of DMA requestor lines Signed-off-by: Olof Johansson <>
2016-04-12Merge tag 'omap-for-v4.6/fixes-rc1' of ↵Olof Johansson-9/+21
git:// into fixes Fixes for omaps against v4.6-rc1. Mostly minor fixes for the newer SoCs with few board fixes and a fix for a long time hwmod bug: - Fix cpsw_emac0 link type for baltos-ir5221 - Fix interrupt type for TWD - Fix edma memcpy channel allocation for am43x - Fix am43x-epos sycntimer32k by using the correct assigned clock - Fix interconnect barrier for dra7 - Fix a long time hwmod bug for updating sysconfig register properly - Fix flakey booting on dm814x where USB reset needs a delay And there is one minor change that is not strictly a fix, but is good to have for proper hardware detection: - Detect dra7 silicon revision 2.0 properly * tag 'omap-for-v4.6/fixes-rc1' of git:// ARM: dts: am335x-baltos-ir5221: fix cpsw_emac0 link type ARM: OMAP: Correct interrupt type for ARM TWD ARM: DRA722: Add ID detect for Silicon Rev 2.0 ARM: dts: am43xx: fix edma memcpy channel allocation ARM: dts: AM43x-epos: Fix clk parent for synctimer ARM: OMAP2: Fix up interconnect barrier initialization for DRA7 ARM: OMAP2+: hwmod: Fix updating of sysconfig register ARM: OMAP2+: Use srst_udelay for USB on dm814x Signed-off-by: Olof Johansson <>
2016-04-12ARM: uniphier: drop weird sizeof()Masahiro Yamada-1/+1
My intention was to ioremap a 4-byte register. Coincidentally enough, sizeof(SZ_4) equals to SZ_4, but this code is weird anyway. Signed-off-by: Masahiro Yamada <> Signed-off-by: Olof Johansson <>
2016-04-11Merge branch 'for-linus' of ↵Linus Torvalds-85/+77
git:// Pull m68k update from Geert Uytterhoeven. * 'for-linus' of git:// m68k/defconfig: Update defconfigs for v4.6-rc2 m68k: Wire up preadv2 and pwritev2
2016-04-11Merge tag 'arc-4.6-rc4-fixes' of ↵Linus Torvalds-9/+21
git:// Pull ARC fixes from Vineet Gupta: - fix Kconfig splat due to pcie rework - make ethernet work again on axs103 - provide fb_pgprotect() for future video driver integration * tag 'arc-4.6-rc4-fixes' of git:// ARC: [plat-axs103] Enable loop block devices Revert "ARC: [plat-axs10x] add Ethernet PHY description in .dts" arc: Add our own implementation of fb_pgprotect() ARC: Don't source drivers/pci/pcie/Kconfig ourselves