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path: root/drivers/crypto/hisilicon/sgl.c
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2020-06-15crypto: hisilicon - Cap block size at 2^31Herbert Xu-1/+2
The function hisi_acc_create_sg_pool may allocate a block of memory of size PAGE_SIZE * 2^(MAX_ORDER - 1). This value may exceed 2^31 on ia64, which would overflow the u32. This patch caps it at 2^31. Reported-by: kernel test robot <lkp@intel.com> Fixes: d8ac7b85236b ("crypto: hisilicon - fix large sgl memory...") Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2019-12-11crypto: hisilicon - Remove useless MODULE macrosZhou Wang-4/+0
As we already merge hardware sgl into hisi_qm module, remove useless MODULE macros. Fixes: 48c1cd40fae3 (crypto: hisilicon - merge sgl support to hisi_qm module) Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2019-12-11crypto: hisilicon - Fix issue with wrong number of sg elements after dma mapJonathan Cameron-5/+8
We fill the hardware scatter gather list assuming it will need the same number of elements at the original scatterlist. If an IOMMU is involved, then it may well need fewer. The return value of dma_map_sg tells us how many. Probably never caused visible problems as the hardware won't get to the elements that are incorrect before it finds enough space. Fixes: dfed0098ab91 (crypto: hisilicon - add hardware SGL support) Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2019-11-01crypto: hisilicon - use sgl API to get sgl dma addr and lenZhou Wang-2/+2
Use sgl API to get sgl dma addr and len, this will help to avoid compile error in some platforms. So NEED_SG_DMA_LENGTH can be removed here, which can only be selected by arch code. Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com> Suggested-by: Herbert Xu <herbert@gondor.apana.org.au> Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2019-10-10crypto: hisilicon - misc fix about sglZhou Wang-18/+22
This patch fixes some misc problems in sgl codes, e.g. missing static, sparse error and input parameter check. Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Shukun Tan <tanshukun1@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2019-10-10crypto: hisilicon - fix large sgl memory allocation problem when disable smmuZhou Wang-15/+68
When disabling SMMU, it may fail to allocate large continuous memory. This patch fixes this by allocating memory as blocks. Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Shukun Tan <tanshukun1@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2019-10-10crypto: hisilicon - add sgl_sge_nr module param for zipShukun Tan-1/+1
Add a module parameter for zip driver to set the number of SGE in one SGL. Signed-off-by: Shukun Tan <tanshukun1@huawei.com> Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2019-10-10crypto: hisilicon - merge sgl support to hisi_qm moduleZhou Wang-39/+34
As HW SGL can be seen as a data format of QM's sqe, we merge sgl code into qm module and rename it as hisi_qm, which reduces the number of module and make the name less generic. This patch also modify the interface of SGL: - Create/free hisi_acc_sgl_pool inside. - Let user to pass the SGE number in one SGL when creating sgl pool, which is better than a unified module parameter for sgl module before. - Modify zip driver according to sgl interface change. Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Shukun Tan <tanshukun1@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2019-08-15crypto: hisilicon - init curr_sgl_dma to fix compile warningZhou Wang-1/+1
Just init curr_sgl_dma = 0 to avoid compile warning. Fixes: dfed0098ab91 ("crypto: hisilicon - add hardware SGL support") Reported-by: kbuild test robot <lkp@intel.com> Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2019-08-09crypto: hisilicon - add hardware SGL supportZhou Wang-0/+214
HiSilicon accelerators in Hip08 use same hardware scatterlist for data format. We support it in this module. Specific accelerator drivers can use hisi_acc_create_sgl_pool to allocate hardware SGLs ahead. Then use hisi_acc_sg_buf_map_to_hw_sgl to get one hardware SGL and pass related information to hardware SGL. The DMA address of mapped hardware SGL can be passed to SGL src/dst field in QM SQE. Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>