path: root/drivers/spi/spi-jcore-bitbang.c

/*
 * SEI SoftCore SPI controller driver
 *
 * Copyright (C) 2012 SEI Inc.
 *		by Oleksandr G Zhadan
 *
 */
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/errno.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/spi/spi.h>
#include <linux/spi/spi_bitbang.h>
#include <linux/io.h>
#include <linux/of.h>

#define DRV_NAME "jcore_bitbang_spi"

#define MAX_SPI_SPEED			12500000	/* 12.5 MHz */

#define CTRL_REG		0x0
#define STAT_REG		0x0
#define DATA_REG		0x4

#define SPI_NOCHIP_CS	0
#define SPI_FLASH_CS	1
#define SPI_CONF_CS	2
#define SPI_SD_CS	2
#define SPI_CODEC_CS	3

#define SEI_SPI_CTRL_ACS		0x01
#define SEI_SPI_CTRL_XMIT		0x02
#define SEI_SPI_STAT_BUSY		0x02
#define SEI_SPI_CTRL_CCS		0x04
#define SEI_SPI_CTRL_LOOP		0x08
#define SEI_SPI_CTRL_DCS		0x10

#define SEI_SPI_WAIT_RDY_MAX_LOOP	2000000	/* in usec */

static unsigned get_sr(void)
{
	unsigned sr;
	__asm__ __volatile__("stc sr,%0" : "=r"(sr));
	return sr;
}

struct sei_spi {
	/* bitbang has to be first */
	struct spi_bitbang bitbang;

	void __iomem *base;
	volatile unsigned int ctrlReg;
	unsigned int csReg;
	unsigned int speedReg;
};

static void sei_spi_wait_till_ready(struct sei_spi *hw, int timeout)
{
	while (timeout--) {
		hw->ctrlReg = readl(hw->base + STAT_REG);
		if (!(hw->ctrlReg & SEI_SPI_STAT_BUSY))
			return;
		cpu_relax();
	}
	pr_err("%s: Timeout..\n", __func__);
}

static void hw_txbyte(struct sei_spi *hw, unsigned char val)
{
	sei_spi_wait_till_ready(hw, SEI_SPI_WAIT_RDY_MAX_LOOP);
	writel(val, hw->base + DATA_REG);
	writel(hw->csReg | hw->speedReg | SEI_SPI_CTRL_XMIT, hw->base + CTRL_REG);
}

static unsigned char hw_rxbyte(struct sei_spi *hw)
{
	sei_spi_wait_till_ready(hw, SEI_SPI_WAIT_RDY_MAX_LOOP);
	return (unsigned char)readl(hw->base + DATA_REG);
}

static void sei_spi_chipsel(struct spi_device *spi, int value)
{
	struct sei_spi *hw = spi_master_get_devdata(spi->master);

//	pr_info("%s: CS=%d cpu=%d\n", __func__, value, smp_processor_id());
	pr_debug("%s: CS=%d\n", __func__, value);

	sei_spi_wait_till_ready(hw, SEI_SPI_WAIT_RDY_MAX_LOOP);

	hw->csReg = ( SEI_SPI_CTRL_ACS | SEI_SPI_CTRL_CCS | SEI_SPI_CTRL_DCS )
		^ (value << 2*spi->chip_select);

	writel(hw->csReg | hw->speedReg, hw->base + CTRL_REG);
}

static void sei_spi_baudrate(struct sei_spi *hw, int speed)
{
	hw->speedReg = ((MAX_SPI_SPEED / speed) - 1) << 27;
	pr_debug("%s: speed=%d pre=0x%x\n", __func__, speed, hw->speedReg);
//	pr_info("%s: speed=%d pre=0x%x\n", __func__, speed, hw->speedReg);
}

static int sei_spi_setupxfer(struct spi_device *spi, struct spi_transfer *t)
{
	struct sei_spi *hw = spi_master_get_devdata(spi->master);
	sei_spi_baudrate(hw, t->speed_hz);
	return 0;
}

static int sei_spi_setup(struct spi_device *spi)
{
	return 0;
}

static int sei_spi_txrx(struct spi_device *spi, struct spi_transfer *t)
{
	struct sei_spi *hw = spi_master_get_devdata(spi->master);

	void *ctrl = hw->base + CTRL_REG;
	void *stat = hw->base + STAT_REG;
	void *data = hw->base + DATA_REG;
	int timeout;
	int xmit = hw->csReg | hw->speedReg | SEI_SPI_CTRL_XMIT;
	int status;

	/* data buffers */
	const unsigned char *tx;
	unsigned char *rx;
	int len;
	int count;

//	pr_info("%s: TXRX cpu=%d\n", __func__, smp_processor_id());

	tx = t->tx_buf;
	rx = t->rx_buf;
	len = t->len;
//	pr_info("txrx %d\n", len);

	for (count = 0; count < len; count++) {
		timeout = SEI_SPI_WAIT_RDY_MAX_LOOP;
		do status = readl(stat);
		while ((status & SEI_SPI_STAT_BUSY) && timeout--);

		writel(tx ? *tx++ : 0, data);
		writel(xmit, ctrl);

		timeout = SEI_SPI_WAIT_RDY_MAX_LOOP;
		do status = readl(stat);
		while ((status & SEI_SPI_STAT_BUSY) && timeout--);

		if (rx) *rx++ = readl(data);
	}
	return count;
}

static int sei_spi_probe(struct platform_device *pdev)
{
	struct device_node *node = pdev->dev.of_node;
	struct sei_spi *hw;
	struct spi_master *master;
	struct resource *res;
	int err = -ENODEV;

	master = spi_alloc_master(&pdev->dev, sizeof(struct sei_spi));
	if (!master)
		return err;

	/* setup the master state. */
	master->bus_num = -1; //pdev->id;
	master->num_chipselect = 3;
	master->mode_bits = SPI_MODE_3;
	master->setup = sei_spi_setup;
	master->transfer = NULL;
	master->dev.of_node = pdev->dev.of_node;

	hw = spi_master_get_devdata(master);
	platform_set_drvdata(pdev, hw);

	/* setup the state for the bitbang driver */
	hw->bitbang.master = spi_master_get(master);
	if (!hw->bitbang.master)
		return err;

	hw->bitbang.setup_transfer = sei_spi_setupxfer;
	hw->bitbang.chipselect = sei_spi_chipsel;
	hw->bitbang.txrx_bufs = sei_spi_txrx;

	/* find and map our resources */
	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!res)
		goto exit_busy;
	if (!devm_request_mem_region
	    (&pdev->dev, res->start, resource_size(res), pdev->name))
		goto exit_busy;
	hw->base =
	    devm_ioremap_nocache(&pdev->dev, res->start, resource_size(res));
	if (!hw->base)
		goto exit_busy;

	sei_spi_baudrate(hw, 400000);

	pdev->dev.dma_mask = 0;
	/* register our spi controller */
	err = spi_bitbang_start(&hw->bitbang);
	if (err)
		goto exit;
	dev_info(&pdev->dev, "base %p, noirq\n", hw->base);

	return 0;

exit_busy:
	err = -EBUSY;
exit:
	platform_set_drvdata(pdev, NULL);
	spi_master_put(master);
	return err;
}

static int sei_spi_remove(struct platform_device *dev)
{
	struct sei_spi *hw = platform_get_drvdata(dev);
	struct spi_master *master = hw->bitbang.master;

	spi_bitbang_stop(&hw->bitbang);
	platform_set_drvdata(dev, NULL);
	spi_master_put(master);
	return 0;
}

static const struct of_device_id jcore_bitbang_of_match[] = {
	{ .compatible = "jcore,soc-spi-0.1" },
	{},
};

static struct platform_driver jcore_bitbang_driver = {
	.probe = sei_spi_probe,
	.remove = sei_spi_remove,
	.driver = {
		.name = DRV_NAME,
		.owner = THIS_MODULE,
		.pm = NULL,
		.of_match_table = jcore_bitbang_of_match,
	},
};

module_platform_driver(jcore_bitbang_driver);

MODULE_DESCRIPTION("J-Core bitbang SPI driver");
MODULE_AUTHOR("Oleksandr G Zhadan <ozhmail@gmail.com>");
MODULE_ALIAS("platform:" DRV_NAME);