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authorRich Felker <dalias@aerifal.cx>2016-01-21 19:08:54 +0000
committerRich Felker <dalias@aerifal.cx>2016-01-21 19:08:54 +0000
commit1315596b510189b5159e742110b504177bdd4932 (patch)
tree27159b7b95b944671454b11f36ee13308241f4b5 /arch/mips/atomic_arch.h
parentce3e24eaae91e7a90f87eb7f1edea8df5942de11 (diff)
downloadmusl-1315596b510189b5159e742110b504177bdd4932.tar.gz
refactor internal atomic.h
rather than having each arch provide its own atomic.h, there is a new shared atomic.h in src/internal which pulls arch-specific definitions from arc/$(ARCH)/atomic_arch.h. the latter can be extremely minimal, defining only a_cas or new ll/sc type primitives which the shared atomic.h will use to construct everything else. this commit avoids making heavy changes to the individual archs' atomic implementations. definitions which are identical or near-identical to what the new shared atomic.h would produce have been removed, but otherwise the changes made are just hooking up the arch-specific files to the new infrastructure. major changes to take advantage of the new system will come in subsequent commits.
Diffstat (limited to 'arch/mips/atomic_arch.h')
-rw-r--r--arch/mips/atomic_arch.h61
1 files changed, 61 insertions, 0 deletions
diff --git a/arch/mips/atomic_arch.h b/arch/mips/atomic_arch.h
new file mode 100644
index 00000000..b111c894
--- /dev/null
+++ b/arch/mips/atomic_arch.h
@@ -0,0 +1,61 @@
+#define a_cas a_cas
+static inline int a_cas(volatile int *p, int t, int s)
+{
+ int dummy;
+ __asm__ __volatile__(
+ ".set push\n"
+ ".set mips2\n"
+ ".set noreorder\n"
+ " sync\n"
+ "1: ll %0, %2\n"
+ " bne %0, %3, 1f\n"
+ " addu %1, %4, $0\n"
+ " sc %1, %2\n"
+ " beq %1, $0, 1b\n"
+ " nop\n"
+ " sync\n"
+ "1: \n"
+ ".set pop\n"
+ : "=&r"(t), "=&r"(dummy), "+m"(*p) : "r"(t), "r"(s) : "memory" );
+ return t;
+}
+
+#define a_swap a_swap
+static inline int a_swap(volatile int *x, int v)
+{
+ int old, dummy;
+ __asm__ __volatile__(
+ ".set push\n"
+ ".set mips2\n"
+ ".set noreorder\n"
+ " sync\n"
+ "1: ll %0, %2\n"
+ " addu %1, %3, $0\n"
+ " sc %1, %2\n"
+ " beq %1, $0, 1b\n"
+ " nop\n"
+ " sync\n"
+ ".set pop\n"
+ : "=&r"(old), "=&r"(dummy), "+m"(*x) : "r"(v) : "memory" );
+ return old;
+}
+
+#define a_fetch_add a_fetch_add
+static inline int a_fetch_add(volatile int *x, int v)
+{
+ int old, dummy;
+ __asm__ __volatile__(
+ ".set push\n"
+ ".set mips2\n"
+ ".set noreorder\n"
+ " sync\n"
+ "1: ll %0, %2\n"
+ " addu %1, %0, %3\n"
+ " sc %1, %2\n"
+ " beq %1, $0, 1b\n"
+ " nop\n"
+ " sync\n"
+ ".set pop\n"
+ : "=&r"(old), "=&r"(dummy), "+m"(*x) : "r"(v) : "memory" );
+ return old;
+}