path: root/arch/riscv64
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authorRich Felker <>2019-05-26 19:27:20 -0400
committerRich Felker <>2019-05-26 19:27:20 -0400
commit5fc43798250255455e4b5f9b08000bd3102274d9 (patch)
tree599d42aaa96840b30de808e67f4fc5cbaa2f55b3 /arch/riscv64
parentac304227bb3ea1787d581f17d76a5f5f3abff51f (diff)
optimize aarch64 dynamic tlsdesc function to spill fewer registers
with the glibc generation counter model for reusing dynamic tls slots after dlclose, it's really not possible to get away with fewer than 4 working registers. for us however it's always been possible, but tricky, and only became apparent after the switch to installing new dynamic tls at dlopen time. by merging the negated thread pointer into the addend early, the register holding the thread pointer can immediately be reused, bringing the working register count down to three. this allows saving/restoring via a single stp/ldp pair, since the return register x0 does not need to be saved. net reduction of 3 instructions, 2 of which were push/pop.
Diffstat (limited to 'arch/riscv64')
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