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authorRich Felker <dalias@aerifal.cx>2019-07-17 19:07:57 -0400
committerRich Felker <dalias@aerifal.cx>2019-07-17 19:07:57 -0400
commitf0eb2e77b2132a88e2f00d8e06ffa7638c40b4bc (patch)
tree55b508243cc3315e6ba981d999d5dc35a0d8d85c /arch/riscv64
parent2dcbeabd917e404a0dde0195388da401b849b9a4 (diff)
downloadmusl-f0eb2e77b2132a88e2f00d8e06ffa7638c40b4bc.tar.gz
use register constraint instead of memory operand for riscv64 atomics
the "A" constraint is simply for an address expression that's a single register, but it's not yet supported by clang, and has no advantage here over just using a register operand for the address. the latter is actually preferable in the a_cas_p case because it avoids aliasing an lvalue onto the memory.
Diffstat (limited to 'arch/riscv64')
-rw-r--r--arch/riscv64/atomic_arch.h16
1 files changed, 8 insertions, 8 deletions
diff --git a/arch/riscv64/atomic_arch.h b/arch/riscv64/atomic_arch.h
index d0228a3e..c9765342 100644
--- a/arch/riscv64/atomic_arch.h
+++ b/arch/riscv64/atomic_arch.h
@@ -9,13 +9,13 @@ static inline int a_cas(volatile int *p, int t, int s)
{
int old, tmp;
__asm__ __volatile__ (
- "\n1: lr.w.aqrl %0, %2\n"
+ "\n1: lr.w.aqrl %0, (%2)\n"
" bne %0, %3, 1f\n"
- " sc.w.aqrl %1, %4, %2\n"
+ " sc.w.aqrl %1, %4, (%2)\n"
" bnez %1, 1b\n"
"1:"
- : "=&r"(old), "=r"(tmp), "+A"(*p)
- : "r"(t), "r"(s)
+ : "=&r"(old), "=r"(tmp)
+ : "r"(p), "r"(t), "r"(s)
: "memory");
return old;
}
@@ -26,13 +26,13 @@ static inline void *a_cas_p(volatile void *p, void *t, void *s)
void *old;
int tmp;
__asm__ __volatile__ (
- "\n1: lr.d.aqrl %0, %2\n"
+ "\n1: lr.d.aqrl %0, (%2)\n"
" bne %0, %3, 1f\n"
- " sc.d.aqrl %1, %4, %2\n"
+ " sc.d.aqrl %1, %4, (%2)\n"
" bnez %1, 1b\n"
"1:"
- : "=&r"(old), "=r"(tmp), "+A"(*(long *)p)
- : "r"(t), "r"(s)
+ : "=&r"(old), "=r"(tmp)
+ : "r"(p), "r"(t), "r"(s)
: "memory");
return old;
}