diff options
| author | Felix Fietkau <nbd@openwrt.org> | 2016-01-25 13:20:52 +0100 |
|---|---|---|
| committer | Rich Felker <dalias@aerifal.cx> | 2016-03-06 17:03:01 -0500 |
| commit | 5a92dd95c77cee81755f1a441ae0b71e3ae2bcdb (patch) | |
| tree | a7a12a71e2a505ed4a5c20c1356fc2d7cf2cb2f1 /src/fenv | |
| parent | 9543656cc32fda48fc463f332ee20e91eed2b768 (diff) | |
| download | musl-5a92dd95c77cee81755f1a441ae0b71e3ae2bcdb.tar.gz | |
add powerpc soft-float support
Some PowerPC CPUs (e.g. Freescale MPC85xx) have a completely different
instruction set for floating point operations (SPE).
Executing regular PowerPC floating point instructions results in
"Illegal instruction" errors.
Make it possible to run these devices in soft-float mode.
Diffstat (limited to 'src/fenv')
| -rw-r--r-- | src/fenv/powerpc/fenv-sf.c | 3 | ||||
| -rw-r--r-- | src/fenv/powerpc/fenv.S (renamed from src/fenv/powerpc/fenv.s) | 42 |
2 files changed, 27 insertions, 18 deletions
diff --git a/src/fenv/powerpc/fenv-sf.c b/src/fenv/powerpc/fenv-sf.c new file mode 100644 index 00000000..85bef40f --- /dev/null +++ b/src/fenv/powerpc/fenv-sf.c @@ -0,0 +1,3 @@ +#ifdef _SOFT_FLOAT +#include "../fenv.c" +#endif diff --git a/src/fenv/powerpc/fenv.s b/src/fenv/powerpc/fenv.S index e34a9990..1516eb5c 100644 --- a/src/fenv/powerpc/fenv.s +++ b/src/fenv/powerpc/fenv.S @@ -1,18 +1,21 @@ +#ifndef _SOFT_FLOAT .global feclearexcept .type feclearexcept,@function feclearexcept: andis. 3,3,0x3e00 - # if (r3 & FE_INVALID) r3 |= all_invalid_flags + /* if (r3 & FE_INVALID) r3 |= all_invalid_flags */ andis. 0,3,0x2000 stwu 1,-16(1) beq- 0,1f oris 3,3,0x01f8 ori 3,3,0x0700 1: - # note: fpscr contains various fpu status and control - # flags and we dont check if r3 may alter other flags - # than the exception related ones - # fpscr &= ~r3 + /* + * note: fpscr contains various fpu status and control + * flags and we dont check if r3 may alter other flags + * than the exception related ones + * ufpscr &= ~r3 + */ mffs 0 stfd 0,8(1) lwz 9,12(1) @@ -21,7 +24,7 @@ feclearexcept: lfd 0,8(1) mtfsf 255,0 - # return 0 + /* return 0 */ li 3,0 addi 1,1,16 blr @@ -30,13 +33,13 @@ feclearexcept: .type feraiseexcept,@function feraiseexcept: andis. 3,3,0x3e00 - # if (r3 & FE_INVALID) r3 |= software_invalid_flag + /* if (r3 & FE_INVALID) r3 |= software_invalid_flag */ andis. 0,3,0x2000 stwu 1,-16(1) beq- 0,1f ori 3,3,0x0400 1: - # fpscr |= r3 + /* fpscr |= r3 */ mffs 0 stfd 0,8(1) lwz 9,12(1) @@ -45,7 +48,7 @@ feraiseexcept: lfd 0,8(1) mtfsf 255,0 - # return 0 + /* return 0 */ li 3,0 addi 1,1,16 blr @@ -54,7 +57,7 @@ feraiseexcept: .type fetestexcept,@function fetestexcept: andis. 3,3,0x3e00 - # return r3 & fpscr + /* return r3 & fpscr */ stwu 1,-16(1) mffs 0 stfd 0,8(1) @@ -66,7 +69,7 @@ fetestexcept: .global fegetround .type fegetround,@function fegetround: - # return fpscr & 3 + /* return fpscr & 3 */ stwu 1,-16(1) mffs 0 stfd 0,8(1) @@ -78,8 +81,10 @@ fegetround: .global __fesetround .type __fesetround,@function __fesetround: - # note: invalid input is not checked, r3 < 4 must hold - # fpscr = (fpscr & -4U) | r3 + /* + * note: invalid input is not checked, r3 < 4 must hold + * fpscr = (fpscr & -4U) | r3 + */ stwu 1,-16(1) mffs 0 stfd 0,8(1) @@ -90,7 +95,7 @@ __fesetround: lfd 0,8(1) mtfsf 255,0 - # return 0 + /* return 0 */ li 3,0 addi 1,1,16 blr @@ -98,10 +103,10 @@ __fesetround: .global fegetenv .type fegetenv,@function fegetenv: - # *r3 = fpscr + /* *r3 = fpscr */ mffs 0 stfd 0,0(3) - # return 0 + /* return 0 */ li 3,0 blr @@ -115,9 +120,10 @@ fesetenv: .zero 8 2: mflr 3 mtlr 4 -1: # fpscr = *r3 +1: /* fpscr = *r3 */ lfd 0,0(3) mtfsf 255,0 - # return 0 + /* return 0 */ li 3,0 blr +#endif |