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authorStefan Kristiansson <stefan.kristiansson@saunalahti.fi>2014-07-17 22:09:10 +0300
committerRich Felker <dalias@aerifal.cx>2014-07-18 14:10:23 -0400
commit200d15479c0bc48471ee7b8e538ce33af990f82e (patch)
tree864cc38895b9277384ed3a956f4ad324de2c4455 /src/ldso
parent7bece9c2095ee81f14b1088f6b0ba2f37fecb283 (diff)
downloadmusl-200d15479c0bc48471ee7b8e538ce33af990f82e.tar.gz
add or1k (OpenRISC 1000) architecture port
With the exception of a fenv implementation, the port is fully featured. The port has been tested in or1ksim, the golden reference functional simulator for OpenRISC 1000. It passes all libc-test tests (except the math tests that requires a fenv implementation). The port assumes an or1k implementation that has support for atomic instructions (l.lwa/l.swa). Although it passes all the libc-test tests, the port is still in an experimental state, and has yet experienced very little 'real-world' use.
Diffstat (limited to 'src/ldso')
-rw-r--r--src/ldso/or1k/dlsym.s5
-rw-r--r--src/ldso/or1k/start.s34
2 files changed, 39 insertions, 0 deletions
diff --git a/src/ldso/or1k/dlsym.s b/src/ldso/or1k/dlsym.s
new file mode 100644
index 00000000..b2f4dfe3
--- /dev/null
+++ b/src/ldso/or1k/dlsym.s
@@ -0,0 +1,5 @@
+.global dlsym
+.type dlsym,@function
+dlsym:
+ l.j plt(__dlsym)
+ l.ori r5, r9, 0
diff --git a/src/ldso/or1k/start.s b/src/ldso/or1k/start.s
new file mode 100644
index 00000000..83b7c2c6
--- /dev/null
+++ b/src/ldso/or1k/start.s
@@ -0,0 +1,34 @@
+.global _dlstart
+_dlstart:
+ l.jal 1f
+ l.nop
+1: l.movhi r5, gotpchi(_GLOBAL_OFFSET_TABLE_+0)
+ l.ori r5, r5, gotpclo(_GLOBAL_OFFSET_TABLE_+4)
+ l.add r5, r5, r9
+ l.movhi r3, gotoffhi(_DYNAMIC)
+ l.ori r3, r3, gotofflo(_DYNAMIC)
+ l.add r5, r5, r3
+
+ l.lwz r3, 0(r1)
+ l.addi r4, r1, 4
+ l.jal plt(__reloc_self)
+ l.addi r1, r1, -16
+
+ l.lwz r3, 16(r1)
+ l.jal plt(__dynlink)
+ l.addi r4, r1, 20
+ l.addi r1, r1, 16
+
+ l.lwz r4, 0(r1)
+1: l.addi r4, r4, -1
+ l.lwz r5, 4(r1)
+ l.sfeqi r5, -1
+ l.bf 1b
+ l.addi r1, r1, 4
+
+ l.addi r4, r4, 1
+ l.addi r1, r1, -4
+ l.sw 0(r1), r4
+
+ l.jr r11
+ l.ori r3, r0, 0