path: root/src/thread/or1k/syscall_cp.s
diff options
authorStefan Kristiansson <>2014-07-17 22:09:10 +0300
committerRich Felker <>2014-07-18 14:10:23 -0400
commit200d15479c0bc48471ee7b8e538ce33af990f82e (patch)
tree864cc38895b9277384ed3a956f4ad324de2c4455 /src/thread/or1k/syscall_cp.s
parent7bece9c2095ee81f14b1088f6b0ba2f37fecb283 (diff)
add or1k (OpenRISC 1000) architecture port
With the exception of a fenv implementation, the port is fully featured. The port has been tested in or1ksim, the golden reference functional simulator for OpenRISC 1000. It passes all libc-test tests (except the math tests that requires a fenv implementation). The port assumes an or1k implementation that has support for atomic instructions (l.lwa/l.swa). Although it passes all the libc-test tests, the port is still in an experimental state, and has yet experienced very little 'real-world' use.
Diffstat (limited to 'src/thread/or1k/syscall_cp.s')
1 files changed, 20 insertions, 0 deletions
diff --git a/src/thread/or1k/syscall_cp.s b/src/thread/or1k/syscall_cp.s
new file mode 100644
index 00000000..02d4cd79
--- /dev/null
+++ b/src/thread/or1k/syscall_cp.s
@@ -0,0 +1,20 @@ __syscall_cp_asm
+.type __syscall_cp_asm,@function
+__syscall_cp_asm: __cp_begin
+ l.lwz r3, 0(r3)
+ l.sfeqi r3, 0
+ l.bnf plt(__cancel)
+ l.ori r11, r4, 0
+ l.ori r3, r5, 0
+ l.ori r4, r6, 0
+ l.ori r5, r7, 0
+ l.ori r6, r8, 0
+ l.lwz r7, 0(r1)
+ l.lwz r8, 4(r1)
+ l.sys 1 __cp_end
+ l.jr r9
+ l.nop