path: root/arch/mips64/reloc.h
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2019-11-05fix build regression on mips64 due to endian.h removalRich Felker-0/+2
commit 4d3a162d001a93edd285fb6603a883c30ae553ba overlooked that the mips64 reloc.h dependent on endian.h not only for setting the ABI ldso name to match the byte order, but also for use of the byte swapping macros. they are needed to override R_TYPE, R_SYM, and R_INFO, to compensate for a mips "quirk" of always using big endian order for symbol references in relocations. part of that commit canot be reverted because the original code was wrong: it's invalid to define _GNU_SOURCE or any feature test macro in reloc.h, or anywhere except at the top of a source file. however, thanks to commit 316730cdc7a330cddf288b4e5c1de5daa64e19f4, the feature test macro is no longer needed to access the endian-swapping macros, so simply bringing back the #include directive suffices.
2019-10-17remove use of endian.h from arch reloc.h headers, clean upRich Felker-8/+0
building on commit 97d35a552ec5b6ddf7923dd2f9a8eb973526acea, __BYTE_ORDER is now available wherever alltypes.h is included. since reloc.h is only used from src/internal/dynlink.h, it can be assumed that __BYTE_ORDER is exposed. reloc.h is not permitted to be included in other contexts, and generally, like most arch headers, lacks inclusion guards that would allow such usage. the mips64 version mistakenly included such guards; they are removed for consistency.
2016-04-03add support for mips and mips64 r6 isaRich Felker-1/+7
mips32r6 and mips64r6 are actually new isas at both the asm source and opcode levels (pre-r6 code cannot run on r6) and thus need to be treated as a new subarch. the following changes are made, some of which yield code generation improvements for non-r6 targets too: - add subarch logic in configure script and reloc.h files for dynamic linker name. - suppress use of .set mips2 asm directives (used to allow mips2 atomic instructions on baseline mips1 builds; the kernel has to emulate them on mips1) except when actually needed. they cause wrong instruction encodings on r6, and pessimize inlining on at least some compilers. - only hard-code sync instruction encoding on mips1. - use "ZC" constraint instead of "m" constraint for llsc memory operands on r6, where the ll/sc instructions no longer accept full 16-bit offsets. - only hard-code rdhwr instruction encoding with .word on targets (pre-r2) where it may need trap-and-emulate by the kernel. otherwise, just use the instruction mnemonic, and allow an arbitrary destination register to be used.
2016-03-06add mips64 portRich Felker-0/+60
patch by Mahesh Bodapati and Jaydeep Patil of Imagination Technologies.