From 6d99ad91e869aab35a4d76d34c3c9eaf29482bad Mon Sep 17 00:00:00 2001
From: Rich Felker <dalias@aerifal.cx>
Date: Sun, 3 Apr 2016 10:42:37 +0000
Subject: add support for mips and mips64 r6 isa

mips32r6 and mips64r6 are actually new isas at both the asm source and
opcode levels (pre-r6 code cannot run on r6) and thus need to be
treated as a new subarch. the following changes are made, some of
which yield code generation improvements for non-r6 targets too:

- add subarch logic in configure script and reloc.h files for dynamic
  linker name.

- suppress use of .set mips2 asm directives (used to allow mips2
  atomic instructions on baseline mips1 builds; the kernel has to
  emulate them on mips1) except when actually needed. they cause wrong
  instruction encodings on r6, and pessimize inlining on at least some
  compilers.

- only hard-code sync instruction encoding on mips1.

- use "ZC" constraint instead of "m" constraint for llsc memory
  operands on r6, where the ll/sc instructions no longer accept full
  16-bit offsets.

- only hard-code rdhwr instruction encoding with .word on targets
  (pre-r2) where it may need trap-and-emulate by the kernel.
  otherwise, just use the instruction mnemonic, and allow an arbitrary
  destination register to be used.
---
 arch/mips/atomic_arch.h | 27 +++++++++++++++++++++++----
 1 file changed, 23 insertions(+), 4 deletions(-)

(limited to 'arch/mips/atomic_arch.h')

diff --git a/arch/mips/atomic_arch.h b/arch/mips/atomic_arch.h
index ce2823b8..1248d177 100644
--- a/arch/mips/atomic_arch.h
+++ b/arch/mips/atomic_arch.h
@@ -1,12 +1,24 @@
+#if __mips_isa_rev < 6
+#define LLSC_M "m"
+#else
+#define LLSC_M "ZC"
+#endif
+
 #define a_ll a_ll
 static inline int a_ll(volatile int *p)
 {
 	int v;
+#if __mips < 2
 	__asm__ __volatile__ (
 		".set push ; .set mips2\n\t"
 		"ll %0, %1"
 		"\n\t.set pop"
 		: "=r"(v) : "m"(*p));
+#else
+	__asm__ __volatile__ (
+		"ll %0, %1"
+		: "=r"(v) : LLSC_M(*p));
+#endif
 	return v;
 }
 
@@ -14,26 +26,33 @@ static inline int a_ll(volatile int *p)
 static inline int a_sc(volatile int *p, int v)
 {
 	int r;
+#if __mips < 2
 	__asm__ __volatile__ (
 		".set push ; .set mips2\n\t"
 		"sc %0, %1"
 		"\n\t.set pop"
 		: "=r"(r), "=m"(*p) : "0"(v) : "memory");
+#else
+	__asm__ __volatile__ (
+		"sc %0, %1"
+		: "=r"(r), "="LLSC_M(*p) : "0"(v) : "memory");
+#endif
 	return r;
 }
 
 #define a_barrier a_barrier
 static inline void a_barrier()
 {
+#if __mips < 2
 	/* mips2 sync, but using too many directives causes
 	 * gcc not to inline it, so encode with .long instead. */
 	__asm__ __volatile__ (".long 0xf" : : : "memory");
-#if 0
-	__asm__ __volatile__ (
-		".set push ; .set mips2 ; sync ; .set pop"
-		: : : "memory");
+#else
+	__asm__ __volatile__ ("sync" : : : "memory");
 #endif
 }
 
 #define a_pre_llsc a_barrier
 #define a_post_llsc a_barrier
+
+#undef LLSC_M
-- 
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