From 6d99ad91e869aab35a4d76d34c3c9eaf29482bad Mon Sep 17 00:00:00 2001 From: Rich Felker Date: Sun, 3 Apr 2016 10:42:37 +0000 Subject: add support for mips and mips64 r6 isa mips32r6 and mips64r6 are actually new isas at both the asm source and opcode levels (pre-r6 code cannot run on r6) and thus need to be treated as a new subarch. the following changes are made, some of which yield code generation improvements for non-r6 targets too: - add subarch logic in configure script and reloc.h files for dynamic linker name. - suppress use of .set mips2 asm directives (used to allow mips2 atomic instructions on baseline mips1 builds; the kernel has to emulate them on mips1) except when actually needed. they cause wrong instruction encodings on r6, and pessimize inlining on at least some compilers. - only hard-code sync instruction encoding on mips1. - use "ZC" constraint instead of "m" constraint for llsc memory operands on r6, where the ll/sc instructions no longer accept full 16-bit offsets. - only hard-code rdhwr instruction encoding with .word on targets (pre-r2) where it may need trap-and-emulate by the kernel. otherwise, just use the instruction mnemonic, and allow an arbitrary destination register to be used. --- arch/mips/reloc.h | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'arch/mips/reloc.h') diff --git a/arch/mips/reloc.h b/arch/mips/reloc.h index 8c52df09..b3d59a45 100644 --- a/arch/mips/reloc.h +++ b/arch/mips/reloc.h @@ -1,5 +1,11 @@ #include +#if __mips_isa_rev >= 6 +#define ISA_SUFFIX "r6" +#else +#define ISA_SUFFIX "" +#endif + #if __BYTE_ORDER == __LITTLE_ENDIAN #define ENDIAN_SUFFIX "el" #else @@ -12,7 +18,7 @@ #define FP_SUFFIX "" #endif -#define LDSO_ARCH "mips" ENDIAN_SUFFIX FP_SUFFIX +#define LDSO_ARCH "mips" ISA_SUFFIX ENDIAN_SUFFIX FP_SUFFIX #define TPOFF_K (-0x7000) -- cgit v1.2.1