From 0b86d60badad6a69b37fc06d18b5763fbbf47b58 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Alex=20R=C3=B8nne=20Petersen?= <alex@alexrp.com>
Date: Sat, 29 Jun 2024 04:04:34 +0200
Subject: riscv: fix setjmp assembly when compiling for ilp32f/lp64f.

per the psABI, floating point register contents beyond the register
size of the targeted ABI variant are never call-saved, so no
hwcap-conditional logic is needed here and the assembly-time
conditions are based purely on ABI variant macros, not the targeted
ISA level.
---
 src/setjmp/riscv32/setjmp.S | 30 ++++++++++++++++++------------
 1 file changed, 18 insertions(+), 12 deletions(-)

(limited to 'src/setjmp/riscv32/setjmp.S')

diff --git a/src/setjmp/riscv32/setjmp.S b/src/setjmp/riscv32/setjmp.S
index 8a75cf55..5a1a41ef 100644
--- a/src/setjmp/riscv32/setjmp.S
+++ b/src/setjmp/riscv32/setjmp.S
@@ -23,18 +23,24 @@ setjmp:
 	sw ra,    52(a0)
 
 #ifndef __riscv_float_abi_soft
-	fsd fs0,  56(a0)
-	fsd fs1,  64(a0)
-	fsd fs2,  72(a0)
-	fsd fs3,  80(a0)
-	fsd fs4,  88(a0)
-	fsd fs5,  96(a0)
-	fsd fs6,  104(a0)
-	fsd fs7,  112(a0)
-	fsd fs8,  120(a0)
-	fsd fs9,  128(a0)
-	fsd fs10, 136(a0)
-	fsd fs11, 144(a0)
+#ifdef __riscv_float_abi_double
+#define FSX fsd
+#else
+#define FSX fsw
+#endif
+
+	FSX fs0,  56(a0)
+	FSX fs1,  64(a0)
+	FSX fs2,  72(a0)
+	FSX fs3,  80(a0)
+	FSX fs4,  88(a0)
+	FSX fs5,  96(a0)
+	FSX fs6,  104(a0)
+	FSX fs7,  112(a0)
+	FSX fs8,  120(a0)
+	FSX fs9,  128(a0)
+	FSX fs10, 136(a0)
+	FSX fs11, 144(a0)
 #endif
 
 	li a0, 0
-- 
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