From 200d15479c0bc48471ee7b8e538ce33af990f82e Mon Sep 17 00:00:00 2001 From: Stefan Kristiansson Date: Thu, 17 Jul 2014 22:09:10 +0300 Subject: add or1k (OpenRISC 1000) architecture port With the exception of a fenv implementation, the port is fully featured. The port has been tested in or1ksim, the golden reference functional simulator for OpenRISC 1000. It passes all libc-test tests (except the math tests that requires a fenv implementation). The port assumes an or1k implementation that has support for atomic instructions (l.lwa/l.swa). Although it passes all the libc-test tests, the port is still in an experimental state, and has yet experienced very little 'real-world' use. --- src/thread/or1k/__set_thread_area.s | 6 ++++++ 1 file changed, 6 insertions(+) create mode 100644 src/thread/or1k/__set_thread_area.s (limited to 'src/thread/or1k/__set_thread_area.s') diff --git a/src/thread/or1k/__set_thread_area.s b/src/thread/or1k/__set_thread_area.s new file mode 100644 index 00000000..44c5d459 --- /dev/null +++ b/src/thread/or1k/__set_thread_area.s @@ -0,0 +1,6 @@ +.global __set_thread_area +.type __set_thread_area,@function +__set_thread_area: + l.ori r10, r3, 0 + l.jr r9 + l.ori r11, r0, 0 -- cgit v1.2.1