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| author | Rich Felker <dalias@aerifal.cx> | 2018-06-14 14:26:30 -0400 |
|---|---|---|
| committer | Rich Felker <dalias@aerifal.cx> | 2018-06-19 13:24:05 -0400 |
| commit | f81e44a0d96c88e052e51982f9fdd6fe0a212b46 (patch) | |
| tree | e8a21317b5af5a2d09543ffcb0fbf1f0a668b63a /src/setjmp | |
| parent | 18f02c42a2b5397e8541f4663eb6ca00c1a806dd (diff) | |
| download | musl-f81e44a0d96c88e052e51982f9fdd6fe0a212b46.tar.gz | |
add m68k port
three ABIs are supported: the default with 68881 80-bit fpu format and
results returned in floating point registers, softfloat-only with the
same format, and coldfire fpu with IEEE single/double only. only the
first is tested at all, and only under qemu which has fpu emulation
bugs.
basic functionality smoke tests have been performed for the most
common arch-specific breakage via libc-test and qemu user-level
emulation. some sysvipc failures remain, but are shared with other big
endian archs and will be fixed separately.
Diffstat (limited to 'src/setjmp')
| -rw-r--r-- | src/setjmp/m68k/longjmp.s | 14 | ||||
| -rw-r--r-- | src/setjmp/m68k/setjmp.s | 18 |
2 files changed, 32 insertions, 0 deletions
diff --git a/src/setjmp/m68k/longjmp.s b/src/setjmp/m68k/longjmp.s new file mode 100644 index 00000000..cdb05fb5 --- /dev/null +++ b/src/setjmp/m68k/longjmp.s @@ -0,0 +1,14 @@ +.global _longjmp +.global longjmp +.type _longjmp,@function +.type longjmp,@function +_longjmp: +longjmp: + movea.l 4(%sp),%a0 + move.l 8(%sp),%d0 + bne 1f + move.l #1,%d0 +1: movem.l (%a0),%d2-%d7/%a2-%a7 + fmovem.x 52(%a0),%fp2-%fp7 + move.l 48(%a0),(%sp) + rts diff --git a/src/setjmp/m68k/setjmp.s b/src/setjmp/m68k/setjmp.s new file mode 100644 index 00000000..15e549b0 --- /dev/null +++ b/src/setjmp/m68k/setjmp.s @@ -0,0 +1,18 @@ +.global ___setjmp +.hidden ___setjmp +.global __setjmp +.global _setjmp +.global setjmp +.type __setjmp,@function +.type _setjmp,@function +.type setjmp,@function +___setjmp: +__setjmp: +_setjmp: +setjmp: + movea.l 4(%sp),%a0 + movem.l %d2-%d7/%a2-%a7,(%a0) + move.l (%sp),48(%a0) + fmovem.x %fp2-%fp7,52(%a0) + clr.l %d0 + rts |